LMH6642, LMH6643, LMH6644
SNOS966P –MAY 2001–REVISED MARCH 2013
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V
IN
(1 V/DIV)
V
A
=±5V, V =5V
IN
S
PP
V
OUT
(2 V/DIV)
100 ns/DIV
=+5, R =R =2k
V
F
L
2 V/DIV
Figure 61. Overload Recovery Waveform
INPUT AND OUTPUT TOPOLOGY
All input / output pins are protected against excessive voltages by ESD diodes connected to V+ and V-rails (see
Figure 62). These diodes start conducting when the input / output pin voltage approaches 1Vbe beyond V+ or V-
to protect against over voltage. These diodes are normally reverse biased. Further protection of the inputs is
provided by the two resistors (R in Figure 62), in conjunction with the string of anti-parallel diodes connected
between both bases of the input stage. The combination of these resistors and diodes reduces excessive
differential input voltages approaching 2Vbe. The most common situation when this occurs is when the device is
used as a comparator (or with little or no feedback) and the device inputs no longer follow each other. In such a
case, the diodes may conduct. As a consequence, input current increases and the differential input voltage is
clamped. It is important to make sure that the subsequent current flow through the device input pins does not
violate the Absolute Maximum Ratings of the device. To limit the current through this protection circuit, extra
series resistors can be placed. Together with the built-in series resistors of several hundred ohms, these external
resistors can limit the input current to a safe number (i.e. < 10mA). Be aware that these input series resistors
may impact the switching speed of the device and could slow down the device.
V+
V+
V+
R
R
IN-
IN+
V-
V-
Figure 62. Input Equivalent Circuit
SINGLE SUPPLY, LOW POWER PHOTODIODE AMPLIFIER
The circuit shown in Figure 63 is used to amplify the current from a photodiode into a voltage output. In this
circuit, the emphasis is on achieving high bandwidth and the transimpedance gain setting is kept relatively low.
Because of its high slew rate limit and high speed, the LMH664X family lends itself well to such an application.
This circuit achieves approximately 1V/mA of transimpedance gain and capable of handling up to 1mApp from the
photodiode. Q1, in a common base configuration, isolates the high capacitance of the photodiode (Cd) from the
Op Amp input in order to maximize speed. Input is AC coupled through C1 to ease biasing and allow single
supply operation. With 5V single supply, the device input/output is shifted to near half supply using a voltage
divider from VCC. Note that Q1 collector does not have any voltage swing and the Miller effect is minimized. D1,
tied to Q1 base, is for temperature compensation of Q1’s bias point. Q1 collector current was set to be large
enough to handle the peak-to-peak photodiode excitation and not too large to shift the U1 output too far from
mid-supply.
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