LMC6482
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SNOS674D –NOVEMBER 1997–REVISED MARCH 2013
A ±7.5V input signal greatly exceeds the 3V supply in Figure 58 causing no phase inversion due to RI.
Figure 57. Input Signal
Applications that exceed this rating must externally limit the maximum input current to ±5mA with an input
resistor (RI) as shown in Figure 58.
RI input current protection for voltages exceeding the supply voltages.
Figure 58. RI Input Current Protection for
Voltages Exceeding the Supply Voltages
RAIL-TO-RAIL OUTPUT
The approximated output resistance of the LMC6482 is 180Ω sourcing and 130Ω sinking at VS = 3V and 110Ω
sourcing and 80Ω sinking at Vs = 5V. Using the calculated output resistance, maximum output voltage swing can
be estimated as a function of load.
CAPACITIVE LOAD TOLERANCE
The LMC6482 can typically directly drive a 100pF load with VS = 15V at unity gain without oscillating. The unity
gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of op-amps.
The combination of the op-amp's output impedance and the capacitive load induces phase lag. This results in
either an under damped pulse response or oscillation.
Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 59. This simple
technique is useful for isolating the capacitive inputs of multiplexers and A/D converters.
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