LMC6482
www.ti.com
SNOS674D –NOVEMBER 1997–REVISED MARCH 2013
DC Electrical Characteristics
Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1M. Boldface limits
apply at the temperature extremes.
LMC6482AI
LMC6482I
LMC6482M
Typ
Parameter
Test Conditions
Limit
Limit
Limit
Units
(1)
(2)
(2)
(2)
VOS
Input Offset Voltage
0.11
0.750
3.0
3.0
mV
1.35
3.7
3.8
max
TCVOS Input Offset Voltage
Average Drift
1.0
μV/°C
(3)
(3)
IB
Input Current
0.02
4.0
2.0
4.0
2.0
10.0
5.0
pA
max
pA
IOS
Input Offset Current
0.01
max
CIN
RIN
Common-Mode Input
Capacitance
3
pF
Input Resistance
>10
82
TeraΩ
CMRR Common Mode Rejection
Ratio
0V ≤ VCM ≤ 15.0V
70
67
65
62
65
60
dB
min
V+ = 15V
0V ≤ VCM ≤ 5.0V
82
82
70
65
65
V+ = 5V
67
62
60
+PSRR Positive Power Supply
Rejection Ratio
5V ≤ V+ ≤ 15V, V− = 0V
70
65
65
dB
min
dB
VO = 2.5V
67
62
60
−PSRR Negative Power Supply
−5V ≤ V− ≤ −15V, V+ = 0V
VO = −2.5V
82
70
65
65
Rejection Ratio
67
62
60
min
V
VCM
Input Common-Mode
Voltage Range
V+ = 5V and 15V
For CMRR ≥ 50dB
V− − 0.3
V+ + 0.3V
666
− 0.25
− 0.25
− 0.25
0
0
0
max
V
V+ + 0.25
V+
V+ + 0.25
V+
V+ + 0.25
V+
min
V/mV
min
V/mV
min
V/mV
min
V/mV
min
(4) (5)
AV
Large Signal Voltage Gain RL = 2kΩ
Sourcing
Sinking
140
84
120
72
120
60
75
35
35
35
20
20
18
(4) (5)
RL = 600Ω
Sourcing
Sinking
300
80
50
50
48
30
25
35
20
15
15
13
10
8
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) Ensured limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
(4) V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 3.5V ≤ VO ≤ 7.5V.
(5) Ensured limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
Copyright © 1997–2013, Texas Instruments Incorporated
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