SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
OVERVIEW
The LM3485 is buck (step-down) DC-DC controller that uses a hysteretic control scheme. The comparator is
designed with approximately 10mV of hysteresis. In response to the voltage at the FB pin, the gate drive
(PGATE pin) turns the external PFET on or off. When the inductor current is too high, the current limit protection
circuit engages and turns the PFET off for approximately 9µs.
Hysteretic control does not require an internal oscillator. Switching frequency depends on the external
components and operating conditions. Operating frequency reduces at light loads resulting in excellent efficiency
compared to other architectures.
2 external resistors can easily program the output voltage. The output can be set in a wide range from 1.242V
(typical) to V
IN
.
HYSTERETIC CONTROL CIRCUIT
The LM3485 uses a comparator based voltage control loop. The feedback is compared to a 1.242V reference
and a 10mV hysteresis is designed into the comparator to ensure noise free operation.
When the FB input to the comparator falls below the reference voltage, the output of the comparator moves to a
low state. This results in the driver output, PGATE, pulling the gate of the PFET low and turning on the PFET.
With the PFET on, the input supply charges Cout and supplies current to the load via the series path through the
PFET and the inductor. Current through the Inductor ramps up linearly and the output voltage increases. As the
FB voltage reaches the upper threshold, which is the internal reference voltage plus 10mV, the output of the
comparator changes from low to high, and the PGATE responds by turning the PFET off. As the PFET turns off,
the inductor voltage reverses, the catch diode turns on, and the current through the inductor ramps down. Then,
as the output voltage reaches the internal reference voltage again, the next cycle starts.
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