SNVS774L – MAY 2004 – REVISED FEBRUARY 2011
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Power Dissipation
Input-Output Voltage Differential
Storage Temperature
Lead Temperature
ESD Tolerance
(1)
(2)
(3)
(3)
Internally Limited
+40V,
−0.3V
−65°C
to +150°C
Metal Package (Soldering, 10 seconds)
Plastic Package (Soldering, 4 seconds)
300°C
260°C
3 kV
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Operating Temperature Range
LM117
LM317A
LM317-N
Preconditioning
Thermal Limit Burn-In
All Devices 100%
−55°C ≤
T
J
≤
+150°C
−40°C ≤
T
J
≤
+125°C
0°C
≤
T
J
≤
+125°C
LM117 Electrical Characteristics
(1)
Specifications with standard type face are for T
J
= 25°C, and those with
boldface type
apply over
full Operating
Temperature Range.
Unless otherwise specified, V
IN
−
V
OUT
= 5V, and I
OUT
= 10 mA.
Parameter
Reference Voltage
Line Regulation
Load Regulation
Thermal Regulation
Adjustment Pin Current
Adjustment Pin Current Change
Temperature Stability
Minimum Load Current
10 mA
≤
I
OUT
≤
I
MAX
3V
≤
(V
IN
−
V
OUT
)
≤
40V
T
MIN
≤
T
J
≤
T
MAX
(V
IN
−
V
OUT
) = 40V
(V
IN
−
V
OUT
)
≤
15V
Current Limit
(V
IN
−
V
OUT
) = 40V
RMS Output Noise, % of V
OUT
10 Hz
≤
f
≤
10 kHz
NDS Package
NDT, NAJ Package
NDS Package
NDT, NAJ Package
1.5
0.5
0.3
0.15
(1)
Conditions
3V
≤
(V
IN
−
V
OUT
)
≤
40V,
10 mA
≤
I
OUT
≤
I
MAX (1)
3V
≤
(V
IN
−
V
OUT
)
≤
40V
10 mA
≤
I
OUT
≤
I
MAX (1)
20 ms Pulse
(3)
LM117
Min
1.20
Typ
1.25
0.01
0.02
0.1
0.3
0.03
50
0.2
1
3.5
2.2
0.8
0.4
0.20
0.003
(2)
Max
1.30
0.02
0.05
0.3
1
0.07
100
5
Units
V
%/V
%
%/W
μA
μA
%
(3)
5
3.4
1.8
mA
A
A
%
(1)
(2)
(3)
4
I
MAX
= 1.5A for the NDS (TO-3), NDE (TO-220), and KTT (TO-263) packages. I
MAX
= 1.0A for the DCY (SOT-223) package. I
MAX
= 0.5A
for the NDT (TO), MDT (PFM), and NAJ (LCCC) packages. Device power dissipation (P
D
) is limited by ambient temperature (T
A
), device
maximum junction temperature (T
J
), and package thermal resistance (θ
JA
). The maximum allowable power dissipation at any
temperature is : P
D(MAX)
= ((T
J(MAX)
- T
A
)/θ
JA
). All Min. and Max. limits are ensured to TI's Average Outgoing Quality Level (AOQL).
Refer to RETS117H drawing for the LM117H, or the RETS117K for the LM117K military specifications.
Regulation is measured at a constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to
heating effects are covered under the specifications for thermal regulation.
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