SNLS384F – FEBRUARY 1995 – REVISED MARCH 2013
(1) (2)
Absolute Maximum Ratings
Supply Voltage
Input Voltage
Output Sink Currents; Pins, 1, 3, 5
Output Sink Current; Pin 7
Package Dissipation
ESD Susceptibility
ESD Susceptibility
(3)
13.2V
3 V
P-P
(V
CC
= 5V)
6 V
P-P
(V
CC
≥
8V)
5 mA
2 mA
1100 mW
−65°C
to +150°C
2 kV
200 V
PDIP Package (10 sec.)
SOIC Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
260°C
215°C
220°C
Storage Temperature Range
(4)
(5)
Soldering Information
(1)
(2)
(3)
(4)
(5)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
For operation in ambient temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a
package thermal resistance of 110°C/W, junction to ambient.
ESD susceptibility test uses the “human body model, 100 pF discharged through a 1.5 kΩ resistor”.
Machine Model, 220 pF – 240 pF discharged through all pins.
Electrical Characteristics LM1881
V
CC
= 5V; R
SET
= 680 kΩ; T
A
= 0°C to +70°C by correlation with 100% electrical testing at T
A
=25°C
Parameter
Supply Current
DC Input Voltage
Input Threshold Voltage
Input Discharge Current
Input Clamp Charge Current
R
SET
Pin Reference Voltage
Composite Sync. & Vertical
Outputs
Outputs at
Logic 1
Pin 2
(2)
Conditions
V
CC
= 5V
V
CC
= 12V
Min
Typ
(1)
Max
10
12
1.8
85
16
1.35
Units
mA
V
mV
µA
mA
V
V
V
V
5.2
5.5
1.3
55
6
0.2
1.10
1.5
70
11
0.8
1.22
4.5
3.6
4.5
0.2
0.2
0.2
0.2
190
230
4
65
2.5
32
Pin 2; V
IN
= 2V
Pin 2; V
IN
= 1V
Pin 6;
(3)
I
OUT
= 40 µA;
Logic 1
I
OUT
= 1.6 mA
Logic 1
V
CC
= 5V
V
CC
= 12V
V
CC
= 5V
V
CC
= 12V
V
CC
= 5V
V
CC
= 12V
4.0
11.0
2.4
10.0
4.0
11.0
Burst Gate & Odd/Even Outputs
Composite Sync. Output
Vertical Sync. Output
Burst Gate Output
Odd/Even Output
Vertical Sync Width
Burst Gate Width
Vertical Default Time
(1)
(2)
(3)
(4)
I
OUT
= 40 µA;
Logic 1
I
OUT
=
−1.6
mA; Logic 0; Pin 1
I
OUT
=
−1.6
mA; Logic 0; Pin 3
I
OUT
=
−1.6
mA; Logic 0; Pin 5
I
OUT
=
−1.6
mA; Logic 0; Pin 7
2.7 kΩ from Pin 5 to V
CC
(4)
0.8
0.8
0.8
0.8
300
4.7
90
V
V
V
V
µs
µs
µs
Typicals are at T
J
= 25°C and represent the most likely parametric norm.
Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.
Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5 and 7) to the R
SET
pin (Pin
6).
Delay time between the start of vertical sync (at input) and the vertical output pulse.
2
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