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SLOS581C – MAY 2008 – REVISED OCTOBER 2009
PARAMETER MEASUREMENT INFORMATION (continued)
A
R VO
B
RE
1 k
W
±1%
S1
C
L
includes fixture
and instrumentation
capacitance
VCC
VI
50%
50%
0V
3V
1.5 V
CL = 15 pF ±20%
t
PZL
50%
10%
t
PLZ
0V
V
CC
V
O
Input
Generator
VI
50
W
Generator: PRR =100 kHz, 50% dutycycle,
tr< 6 ns, t f < 6ns, ZO= 50
W
VOL
Figure 10. Receiver Enable Test Circuit and Waveforms, Data Output Low
0V
A
B
Pulse Generator
15
m
s duration
1% duty cycle
t
r
, t
f
£
100 ns
RE
R
100
W
±1%
+
_
D
DE
3V
Note:This test is conducted to test survivability only.
Data stability at the R output is not specified.
Figure 11. Transient Over-Voltage Test Circuit
2V
C = 0.1
m
F
±
1%
V
CC1
DE
GND1
S1
B
D
V
CC2
A
C = 0.1
m
F
±
1%
54
W
V
OH
or V
OL
0.8 V
R
V
OH
or V
OL
1 kW
RE
GND1
CL = 15 pF
(includes probe and
jig capacitance)
GND2
V TEST
Figure 12. Half-Duplex Common-Mode Transient Immunity Test Circuit
Copyright © 2008–2009, Texas Instruments Incorporated
7
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