HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
PCI timing requirements over recommended ranges of supply voltage and operating free–air
†
temperature (see Note 3)
ALTERNATE
PARAMETER
TEST CONDITIONS
= 50 pF,
See Note 4,
1,2,3
MIN
MAX UNITS
SYMBOL
C
L
PCLK to shared signal valid delay
time
t
pd
Propagation delay time
t
2
2
11
28
ns
val
t
t
t
t
Enable time, high-impedance-to-active delay time from PCLK
Disable time, active-to-high-impedance delay time from PCLK
Valid setup time, before PCLK
t
on
ns
ns
ns
ns
en
dis
su
h
t
off
t
su
3,4
4
3
0
Hold time, after PCLK high
t
h
†
Applies to external output buffers.
NOTES: 3. This data sheet uses the following conventions to describe time ( t ) intervals. The format is: t , where subscript A indicates the type
A
ofdynamicparameterbeingrepresented. Oneofthefollowingisused:t =propagationdelaytime, t = delay time, t =setuptime,
pd su
d
and t = hold time.
h
4. PCI shared signals are AD31–AD0, C/BE3–C/BE0, PCIFRAME, PCITRDY, PCIIRDY, PCISTOP, IDSEL, PCIDEVSEL, and
PCIPAR.
†
serial bus interface
STANDARD
MODE
FAST MODE
UNIT
MIN
0
MAX
MIN
0
MAX
f
t
SCL clock frequency (see Note 5)
100
400
kHz
SCL
Bus free time between a STOP and START condition
4.7
1.3
µs
BUF
Hold time (repeated) START condition. After this period, the first clock pulse is
generated.
t
4
0.6
µs
HD;STA
t
t
t
LOW period of the SCL clock
4.7
4
1.3
0.6
0.6
µs
µs
µs
LOW
HIGH period of the SCL clock
HIGH
Setup time for a repeated START condition
For CBUS compatible masters:
4.7
5
SU;STA
t
Data hold time (see Note 6)
µs
HD;DAT
For serial bus devices:
0
1
0
1
0.9
2
t
t
t
t
Data setup time (see Note 7)
250
100
µs
µs
µs
µs
SU;DAT
3
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
1000
300
20
20
300
300
R
F
4
0.6
FSU;STO
†
All values refer to serial bus interface V
IH MIN
and V
levels
IL MAX
NOTES: 5. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
to bridge the undefined region of the falling edge of SCL.
of the SCL signal) in order
IH MIN
6. The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SDL signal.
> 250 ns must then
HD;DAT
LOW
7. A fast mode serial bus device can be used in a standard mode serial bus system, but the requirement t
SU;DAT
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t + t = 1000 + 250 = 1250 ns
R MAX SU;DAT
(according to the Standard Mode Serial Bus Specification) before the SCL line is released.
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
