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DS90CR285MTD 参数 Datasheet PDF下载

DS90CR285MTD图片预览
型号: DS90CR285MTD
PDF下载: 下载PDF文件 查看货源
内容描述: DS90CR285 / DS90CR286 3.3V上升沿数据选通LVDS 28位通道链接-66 MHz的 [DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
文件页数/大小: 25 页 / 1191 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SNLS130C – MARCH 1999 – REVISED MARCH 2013
DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
Check for Samples:
1
FEATURES
Single +3.3V Supply
Chipset (Tx + Rx) Power Consumption <250
mW (typ)
Power-Down Mode (<0.5 mW total)
Up to 231 Megabytes/sec Bandwidth
Up to 1.848 Gbps Data Throughput
Narrow Bus Reduces Cable Size
290 mV Swing LVDS Devices for Low EMI
+1V Common Mode Range (Around +1.2V)
PLL Requires no External Components
Both Devices are Offered in a Low Profile 56-
Lead TSSOP Package
Rising Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
ESD Rating > 7 kV
Operating Temperature:
−40°C
to +85°C
DESCRIPTION
The DS90CR285 transmitter converts 28 bits of
LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fifth LVDS link. Every cycle of the
transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR286 receiver converts the
LVDS data streams back into 28 bits of
LVCMOS/LVTTL data. At a transmit clock frequency
of 66 MHz, 28 bits of TTL data are transmitted at a
rate of 462 Mbps per LVDS data channel. Using a 66
MHz clock, the data throughput is 1.848 Gbit/s (231
Mbytes/s).
The multiplexing of the data lines provides a
substantial cable reduction. Long distance parallel
single-ended buses typically require a ground wire
per active signal (and have very limited noise
rejection capability). Thus, for a 28-bit wide data and
one clock, up to 58 conductors are required. With the
Channel Link chipset as few as 11 conductors (4 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required
cable width, which provides a system cost savings,
reduces connector physical size and cost, and
reduces shielding requirements due to the cables'
smaller form factor.
The 28 LVCMOS/LVTTL inputs can support a variety
of signal combinations. For example, seven 4-bit
nibbles or three 9-bit (byte + parity) and 1 control.
2
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 1999–2013, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.