SNLS130C – MARCH 1999 – REVISED MARCH 2013
Transmitter Switching Characteristics
Over recommended operating supply and
−40°C
to +85°C ranges unless otherwise specified
Symbol
LLHT
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
(1)
(2)
Parameter
LVDS Low-to-High Transition Time (Figure
6)
LVDS High-to-Low Transition Time (Figure
6)
TxCLK IN Transition Time (Figure
8)
TxOUT Channel-to-Channel Skew (Figure
9)
Transmitter Output Pulse Position for Bit0
(1)
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
Transmitter Output Pulse Position for Bit0
(2)
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
TxCLK IN Period
)
TxCLK IN High Time (Figure
TxCLK IN Low Time (Figure
TxIN Setup to TxCLK IN (Figure
TxIN Hold to TxCLK IN (Figure
TxCLK IN to TxCLK OUT Delay @ 25°C,V
CC
=3.3V (Figure
Transmitter Phase Lock Loop Set (Figure
Transmitter Powerdown Delay (Figure
f = 66 MHz
f = 40 MHz
−0.4
3.1
6.5
10.2
13.7
17.3
21.0
−0.4
1.8
4.0
6.2
8.4
10.6
12.8
15
0.35T
0.35T
2.5
0
3
3.7
5.5
10
100
250
0
3.3
6.8
10.4
13.9
17.6
21.2
0
2.2
4.4
6.6
8.8
11.0
13.2
T
0.5T
0.5T
0.4
4.0
7.6
11.0
14.6
18.2
21.8
0.3
2.5
4.7
6.9
9.1
11.3
13.5
50
0.65T
0.65T
Min
Typ
0.5
0.5
Max
1.5
1.5
5
Units
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
The min. and max. limits are based on the worst bit by applying a
−400ps/+300ps
shift from ideal position.
Receiver Switching Characteristics
Over recommended operating supply and
−40°C
to +85°C ranges unless otherwise specified
Symbol
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
Parameter
CMOS/TTL Low-to-High Transition Time (Figure
7)
CMOS/TTL High-to-Low Transition Time (Figure
7)
Receiver Input Strobe Position for Bit 0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
(1)
Min
Typ
2.2
2.2
Max
5.0
5.0
2.15
5.8
9.15
12.6
16.3
19.9
23.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
f = 40 MHz
1.0
4.5
8.1
11.6
15.1
18.8
22.5
1.4
5.0
8.5
11.9
15.6
19.2
22.9
(1)
The min. and max. are based on the actual bit position of each of the 7 bits within the LVDS data stream across PVT.
5
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links:
TI [ TEXAS INSTRUMENTS ]
