SNLS130C – MARCH 1999 – REVISED MARCH 2013
Receiver Switching Characteristics (continued)
Over recommended operating supply and
−40°C
to +85°C ranges unless otherwise specified
Symbol
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
Receiver Input Strobe Position for Bit 0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin
(3)
(2)
Min
f = 66 MHz
0.7
2.9
5.1
7.3
9.5
11.7
13.9
f = 40 MHz
f = 66 MHz
490
400
15
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
6.0
4.0
10.0
6.0
6.5
2.5
6.0
2.5
4.0
5.0
Typ
1.1
3.3
5.5
7.7
9.9
12.1
14.3
Max
1.4
3.6
5.8
8.0
10.2
12.4
14.6
Units
ns
ns
ns
ns
ns
ns
ns
ps
ps
RxCLK OUT Period (Figure
RxCLK OUT High Time (Figure
RxCLK OUT Low Time (Figure
RxOUT Setup to RxCLK OUT (Figure
RxOUT Hold to RxCLK OUT (Figure
RxCLK IN to RxCLK OUT Delay (Figure
Receiver Phase Lock Loop Set (Figure
Receiver Powerdown Delay (Figure
T
10.0
6.1
13.0
7.8
14.0
8.0
8.0
4.0
6.7
6.6
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
8.0
9.0
10
1
ns
ns
ms
μs
(2)
(3)
The min. and max. limits are based on the worst bit by applying a
−400ps/+300ps
shift from ideal position.
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS
interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter less than 250 ps).
AC TIMING DIAGRAMS
Figure 5. “Worst Case” Test Pattern
6
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