SNLS128C – APRIL 1999 – REVISED FEBRUARY 2013
DS26LV32AT 3V Enhanced CMOS Quad Differential Line Receiver
Check for Samples:
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FEATURES
Low Power CMOS Design (30 mW typical)
Interoperable with Existing 5V RS-422
Networks
Industrial and Military Temperature Range
Conforms to TIA/EIA-422-B (RS-422) and ITU-T
V.11 Recommendation
3.3V Operation
±7V Common Mode Range @ V
ID
= 3V
±10V Common Mode Range @ V
ID
= 0.2V
Receiver OPEN Input Failsafe Feature
Guaranteed AC Parameter:
–
Maximum Receiver Skew: 4 ns
–
Maximum Transition Time: 10 ns
Pin Compatible with DS26C32AT
32 MHz Toggle Frequency
> 6.5k ESD Tolerance (HBM)
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Available in SOIC and CLGA Packaging
Standard Microcircuit Drawing (SMD) 5962-
98585
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DESCRIPTION
The DS26LV32A is a high speed quad differential
CMOS receiver that meets the requirements of both
TIA/EIA-422-B and ITU-T V.11. The CMOS
DS26LV32AT features typical low static I
CC
of 9 mA
which makes it ideal for battery powered and power
conscious applications. The TRI-STATE enables, EN
and EN*, allow the device to be active High or active
Low. The enables are common to all four receivers.
The receiver output (RO) is guaranteed to be High
when the inputs are left open. The receiver can
detect signals as low as ±200 mV over the common
mode range of ±10V. The receiver outputs (RO) are
compatible with TTL and LVCMOS levels.
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Connection Diagram
Top View
Figure 1.
SOIC Package
See Package Numbers D0016A or NAD0016A
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PRODUCTION DATA information is current as of publication date.
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