SLES256 – MAY 2010
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During T_OC Period
PVDD
CBC with Low Side OC
Current Limit
PWM_HS
Load
Current
Load
PWM_LS
GND_X
PWM_HS
PWM_LS
T_LS T_OC T_HS
Figure 7. Cycle-by-Cycle Operation with Low Side OC (dashed line: normal operation; solid line: CBC
event)
GVDD
330
m
F
1
m
F
DRV8332
GVDD_B
OTW
FAULT
PWM_A
RESET_A
GVDD_A
BST_A
100 nF
PVDD_A
OUT_A
Rsense_A
GND_A
Rsense_B
PWM_B
Roc_adj
OC_ADJ
1
GND
AGND
100 nF
VREG
M3
M2
M1
RESET_B
RESET_C
PWM_C
NC
NC
GND
GND
Rsense_C
GND_C
OUT_C
PVDD_C
BST_C
GVDD_C
100 nF
OUT_B
PVDD_B
BST_B
100 nF
GND_B
1
m
F
3.3
PVDD
1000
m
F
10 nF
Loc
100nF
Controller
(MSP430
C2000 or
Stellaris MCU)
M
Loc
100nF
Rsense_x
£
10 mW
or
Vsense < 100 mV
Loc
GVDD
47
m
F
1
m
F
1
m
F
VDD
GVDD_C
100nF
PVDD
Figure 8. DRV8332 Application Diagram for Three-Phase Operation
14
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