6 0 Pin Descriptions
28-Pin PLCC
2
3
16-Pin DIP
1
2
Name
CD
a
CD
b
I O
O
Description
Collision Output
Balanced differential line driver outputs from the collision detect
circuitry The 10 MHz signal from the internal oscillator is transferred to these
outputs in the event of collision excessive transmission (jabber) or during CD
Heartbeat condition These outputs are open emitters pulldown resistors to VEE
are required When operating into a 78X transmission line these resistors should
be 500X In Cheapernet applications where the 78X drop cable is not used
higher resistor values (up to 1 5k) may be used to save power
Receive Output
Balanced differential line driver outputs from the Receiver These
outputs also require 500X pulldown resistors
Transmit Input
Balanced differential line receiver inputs to the Transmitter The
common mode voltage for these inputs is determined internally and must not be
externally established Signals meeting Transmitter squelch requirements are
waveshaped and output at TXO
Heartbeat Enable
This input enables CD Heartbeat when grounded disables it
when connected to VEE
4
12
13
14
3
6
7
8
RX
a
RX
b
TX
a
TX
b
O
I
15
18
19
26
9
11
12
14
HBE
RR
a
RR
b
RXI
I
I
I
Receive Input
Connects directly to the coaxial cable Signals meeting Receiver
squelch requirements are equalized for inter-symbol distortion amplified and
outputted at RX
g
Transmit Output
Connects either directly (Cheapernet) or via an isolation diode
(Ethernet) to the coaxial cable
Collision Detect Sense
Ground sense connection for the collision detect circuit
This pin should be connected separately to the shield to avoid ground drops from
altering the receive mode collision threshold
Positive Supply Pin
A 0 1
mF
ceramic decoupling capacitor must be connected
across GND and VEE as close to the device as possible
28
1
15
16
TXO
CDS
O
I
16 17
5–11
20–25
10
4
5
13
GND
VEE
IEEE names for CD
g
e
CI
g
RX
g
e
DI
g
TX
g
e
DO
g
6 1 P C BOARD LAYOUT
The DP8392C package is uniquely designed to ensure that
the device meets the 1 million hour Mean Time Between
Failure (MTBF) requirement of the IEEE 802 3 standard In
order to fully utilize this heat dissipation design the three
V
EE
pins are to be connected to a copper plane which
should be included in the printed circuit board layout
There are two basic considerations in designing a PCB for
the DP8392C and C-1 CTI The first is ensuring that the
layout does not degrade the electrical characteristics of the
DP8392 and enables the end product to meet the IEEE
802 3 specifications The second consideration is meeting
the thermal requirements to the DP8392
Since the DP8392 is highly integrated the layout is actually
quite simple and there are just a few guidelines
1 Ensure that the parasitic capacitance added to the RXI
and TXO pins is minimized To do this keep these signal
traces short and remove any power planes under these
signals and under any components that connect to these
signals
Figure 6
shows the component placement for the
DIP package The PLCC component placement would be
similar as shown in
Figure 7
O
bs
ol
5
Negative Supply Pins
In order to make full use of the 3 5W power dissipation
capability of this package these pins should be connected to a large metal frame
area on the PC board Doing this will reduce the operating die temperature of the
device thereby increasing the long term reliability
et
2 The power supply layout to the CTI should be relatively
clean Usually the CTI’s power is supplied directly by a
DC-DC converter The power should be routed either
through separate isolated planes or via thick PCB traces
For the second consideration the packaged DP8392 must
have a thermal resistance of 40 C– 45 C W to meet the full
0 C–70 C temperature range The CTI dissipates more
power when transmitting than while it is idle In order to do
this the thermal resistance of the device must be 40 C –
45 C W To meet this requirement during transmission it is
recommended that a small printed circuit board plane be
connected to all V
EE
pins on the solder side of the PCB
The size of the trace plane depends on the package used
and the duty cycle of transmissions For the DIP package
the plane should be connected to pins 4 – 5 13 and the size
should be approximately 0 2 square inches for applications
where the duty cycle of the transmitter is very low (
k
10%)
This would be typical of adapter or motherboard applica-
tions In applications where the transmitter duty cycle may
be large (repeaters and external transceivers) the total area
should be increased to 0 4 in
2
Figure 6
illustrates a recom-
mended component side layout for these planes
e
External Resistor
A fixed 1k 1% resistor connected between these pins
establishes internal operating currents
TI [ TEXAS INSTRUMENTS ]
