DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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32-bit DDR3 EMIF
8-Bit DDR3
Devices
8-Bit DDR3
Devices
DDR[0]_D[31]
8
DQ7
DQ0
DDR[0]_D[24]
DDR[0]_DQM[3]
DM/TQS
TDQS
DQS
NC
DDR[0]_DQS[3]
DDR[0]_DQS[3]
DQS
DDR[0]_D[23]
8
DQ7
DQ0
DDR[0]_D[16]
DDR[0]_DQM[2]
DM/TQS
TDQS
DQS
NC
DDR[0]_DQS[2]
DDR[0]_DQS[2]
DQS
DDR[0]_D[15]
8
DQ7
DQ0
DDR[0]_D[8]
DDR[0]_DQM[1]
DM/TQS
TDQS
DQS
NC
DDR[0]_DQS[1]
DDR[0]_DQS[1]
DQS
DDR[0]_D[7]
DQ7
DQ0
8
DDR[0]_D[0]
DDR[0]_DQM[0]
DM/TQS
TDQS
DQS
NC
DDR[0]_DQS[0]
DDR[0]_DQS[0]
DQS
0.1 µF
Zo
Zo
DDR[0]_CLK
DDR[0]_CLK
CK
CK
CK
CK
CK
CK
CK
CK
DVDD_DDR[0]
DDR[0]_ODT[0]
DDR[0]_CS[0]
DDR[0]_BA[0]
DDR[0]_BA[1]
DDR[0]_BA[2]
ODT
ODT
ODT
ODT
CS
CS
CS
CS
BA0
BA1
BA2
BA0
BA1
BA2
BA0
BA1
BA2
BA0
BA1
BA2
DDR_VTT
Zo
Zo
DDR[0]_A[0]
A0
A0
A0
A0
16
DDR[0]_A[15]
A15
A15
A15
A15
DDR[0]_CAS
DDR[0]_RAS
DDR[0]_WE
DDR[0]_CKE
DDR[0]_RST
CAS
CAS
RAS
WE
CAS
CAS
RAS
WE
RAS
RAS
WE
WE
CKE
CKE
RST
CKE
CKE
RST
RST
RST
DDR_VREF
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFSSTL_DDR[0]
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
DDR[0]_VTP
50 Ω ( 2%)
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
Figure 8-57. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices
232
Peripheral Information and Timings
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