DM385, DM388
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32-bit DDR3 EMIF
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
16-Bit DDR3
Devices
DDR[0]_D[31]
DQ15
8
DDR[0]_D[24]
DQ8
DDR[0]_DQM[3]
DDR[0]_DQS[3]
DDR[0]_DQS[3]
UDM
UDQS
UDQS
DDR[0]_D[23]
DQ7
8
DDR[0]_D[16]
D08
DDR[0]_DQM[2]
DDR[0]_DQS[2]
DDR[0]_DQS[2]
LDM
LDQS
LDQS
DDR[0]_D[15]
DQ15
DQ8
8
DDR[0]_D[8]
DDR[0]_DQM[1]
DDR[0]_DQS[1]
DDR[0]_DQS[1]
UDM
UDQS
UDQS
DDR[0]_D[7]
DQ7
8
DDR[0]_D[0]
DQ0
DDR[0]_DQM[0]
DDR[0]_DQS[0]
DDR[0]_DQS[0]
LDM
LDQS
LDQS
0.1 µF
Zo
Zo
DDR[0]_CLK
DDR[0]_CLK
CK
CK
CK
CK
DVDD_DDR[0]
DDR[0]_ODT[0]
DDR[0]_CS[0]
DDR[0]_BA[0]
DDR[0]_BA[1]
DDR[0]_BA[2]
ODT
ODT
CS
CS
BA0
BA1
BA2
BA0
BA1
BA2
DDR_VTT
Zo
Zo
DDR[0]_A[0]
A0
A0
16
DDR[0]_A[15]
DDR[0]_CAS
A15
A15
CAS
CAS
RAS
WE
DDR[0]_RAS
DDR[0]_WE
DDR[0]_CKE
DDR[0]_RST
RAS
WE
CKE
CKE
RST
DDR_VREF
RST
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFSSTL_DDR[0]
0.1 µF
0.1 µF
0.1 µF
DDR[0]_VTP
50 Ω ( 2%)
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
Figure 8-56. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
231
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