PIN CONFIGURATION
Top View
TQFP
CAP1A
CAP1A
AVDD
NC
1
2
3
4
5
6
7
8
24 CAP2A
23 CAP2A
22 VREF
21 AGND
20 NC
DDC112Y
NC
TEST
CONV
CLK
19 NC
18 RANGE2 (MSB)
17 RANGE1
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
PIN
LABEL
DESCRIPTION
1
2
3
4
5
6
CAP1A
CAP1A
AVDD
NC
External Capacitor for Integrator 1A
External Capacitor for Integrator 1A
Analog Supply, +5V Nominal
No Connection
15
DVALID Data Valid Output. A LOW value indicates valid data is
available in the serial I/O register.
16
17
18
19
20
21
22
23
24
25
26
27
28
RANGE0 Range Control Input 0 (least significant bit)
RANGE1 Range Control Input 1
RANGE2 Range Control Input 2. (most significant bit)
NC
No Connection
NC
No Connection
TEST
Test Control Input. When HIGH, a test charge is
applied to the A or B integrators on the next CONV
transition.
NC
No Connection
AGND
VREF
Analog Ground
7
CONV
Controls which side of the integrator is connected to
input. In continuous mode; CONV HIGH side A is
integrating, CONV LOW side B is integrating CONV
must be synchronized with CLK (see text).
External Reference Input, +4.096V Nominal
External Capacitor for Integrator 2A
External Capacitor for Integrator 2A
External Capacitor for Integrator 2B
External Capacitor for Integrator 2B
Analog Ground
CAP2A
CAP2A
CAP2B
CAP2B
AGND
IN2
8
9
CLK
System Clock Input, 10MHz Nominal
DCLK
Serial Data Clock Input. This input operates the
serial I/O shift register.
10
11
DXMIT
DIN
Serial Data Transmit Enable Input. When LOW, this
input enables the internal serial shift register.
Input 2: analog input for Integrators 2A and 2B. The
integrator that is active is set by the CONV input.
Serial Digital Input. Used to cascade multiple
DDC112s.
29
IN1
Input 1: analog input for Integrators 1A and 1B. The
integrator that is active is set by the CONV input.
12
13
14
DVDD
DGND
DOUT
Digital Supply, +5V Nominal
Digital Ground
30
31
32
AGND
CAP1B
CAP1B
Analog Ground
External Capacitor for Integrator 1B
External Capacitor for Integrator 1B
Serial Data Output, Hi-Z when DXMIT is HIGH
DDC112
SBAS085B
5
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