PIN CONFIGURATION
Top View
SO, TSSOP
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DESIGNATOR
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
NC
NC
NC
NC
PD
DESCRIPTION
Data Bit 1 (D9), MSB
Data Bit 2 (D8)
Data Bit 3 (D7)
Data Bit 4 (D6)
Data Bit 5 (D5)
Data Bit 6 (D4)
Data Bit 7 (D3)
Data Bit 8 (D2)
Data Bit 9 (D1)
Data Bit 10 (D0), LSB
No Connection
No Connection
No Connection
No Connection
Power Down, Control Input; Active
HIGH. Contains internal pull-down circuit;
may be left unconnected if not used.
Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation.
Reference Input/Ouput. See Applications
section for further details.
Full-Scale Output Adjust
Bandwidth/Noise Reduction Pin:
Bypass with 0.1µF to +V
A
for Optimum
Performance.
Analog Ground
Complementary DAC Current Output
DAC Current Output
Bypass Node: Use 0.1µF to AGND
Analog Supply Voltage, 2.7V to 5.5V
No Connection
Digital Ground
Digital Supply Voltage, 2.7V to 5.5V
Clock Input
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
1
2
3
4
5
6
7
DAC900
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK
+V
D
DGND
NC
+V
A
BYP
I
OUT
I
OUT
AGND
BW
FSA
REF
IN
INT/EXT
PD
16
17
18
19
INT/EXT
REF
IN
FSA
BW
Bit 10 10
NC 11
NC 12
NC 13
NC 14
20
21
22
23
24
25
26
27
28
AGND
I
OUT
I
OUT
BYP
+V
A
NC
DGND
+V
D
CLK
TYPICAL CONNECTION CIRCUIT
+5V
0.1µF
+V
A
DAC900
FSA
REF
IN
R
SET
0.1µF
Current
Sources
LSB
Switches
Segmented
MSB
Switches
BW
+V
D
I
OUT
I
OUT
BYP
0.1µF
50Ω
20pF
50Ω
20pF
1:1
+5V
INT/EXT
PD
Latches
+1.24V Ref.
10-Bit Data Input
AGND
CLK
D9.......D0
DGND
4
DAC900
SBAS093B
TI [ TEXAS INSTRUMENTS ]
