DAC8571
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SLAS373A–DECEMBER 2002–REVISED JULY 2003
THEORY OF OPERATION (continued)
Table 1. Master Transmitter Writing to Slave Receiver (DAC8571)
Standard/Fast Mode Write Sequence - Data Input
Transmitter
Master
MSB
6
0
5
0
4
3
2
1
0
LSB
R/W
PD0
D8
Comment
Start
Begin sequence
Master
1
1
1
A0
Write addressing (LSB=0)
Control byte (PD0=0)
Writing dataword, high byte
Writing dataword, low byte
Done
DAC8571
Master
DAC8571 Acknowledges
Load 0
DAC8571 Acknowledges
D12 D11
DAC8571 Acknowledges
D4 D3
DAC8571 Acknowledges
(1) (2)
0
0
Load 1
D13
D5
0
Brcsel
D10
D2
0
DAC8571
Master
D15
D7
D14
D6
D9
D1
DAC8571
Master
D0
DAC8571
Master
Stop or Repeated Start
Standard/Fast Mode Write Sequence-Power Down Input
Transmitter
Master
MSB
6
5
4
3
2
A0
1
0
0
0
0
LSB
R/W
PD0
0
Comment
Start
Begin sequence
Write addressing (LSB=0)
Master
1
0
0
1
1
DAC8571
Master
DAC8571 Acknowledges
Load 0
DAC8571 Acknowledges
0
0
Load 1
PD3
0
0
Brcsel
0
Control byte (PD0=1)
Writing dataword, high byte
Writing dataword, low byte
Done
DAC8571
Master
PD1
0
PD2
0
0
0
DAC8571
Master
DAC8571 Acknowledges
0
0
0
0
DAC8571
Master
DAC8571 Acknowledges
(3) (4)
Stop or Repeated Start
(1)
(2)
(3)
(4)
High byte, low byte sequence can repeat.
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
High byte, low byte sequence can repeat.
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
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