DAC7802
BLOCK DIAGRAM
PIN CONFIGURATION
Top View
DIP
VDD
21
1
2
24
23
22
21
20
19
18
17
16
15
14
13
AGND
IOUT A
RFB A
IOUT B
RFB B
VREF B
VDD
12
DAC7802
CK DAC A Register
12
3
2
3
4
IOUT A
RFB A
VREF A
4
DAC A
VREF A
CS A
5
CS A
5
CS B
WR
6
(LSB) DB0
DB1
DAC7802
22 VREF B
23 RFB B
24 IOUT B
7
DB11 (MSB)
DB10
DB9
8
DB2
DAC B
CS B 20
WR 19
9
DB3
1
AGND
12
10
11
12
DB4
DB8
CK DAC B Register
12
DB5
DB7
DGND
DB6
12
18
DB11–DB0
6
DGND
TIMING CHARACTERISTICS
At VDD = +5V, and TA = –40oC to +85oC.
t1
t2
5V
0V
DATA
t3
t4
PARAMETER
MINIMUM
5V
CSA, CSB
t
t
t
t
t
1 - Data Setup Time
2 - Data Hold Time
3 - Chip Select to Write Setup Time
4 - Chip Select to Write Hold Time
5 - Write Pulse Width
20ns
15ns
30ns
0ns
t5
5V
WR
NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. tR = tR = 5ns. (2) Timing measurement reference level
30ns
V
IH + VIL
is
.
2
LOGIC TRUTH TABLE
CSA
CSB
WR
FUNCTION
X
1
X
1
1
X
0
No Data Transfer
No Data Transfer
A Rising Edge on CSA or CSB Loads
Data to the Respective DAC
0
1
0
1
0
0
DAC A Register Loaded from Data Bus
DAC B Register Loaded from Data Bus
DAC A and DAC B Registers Loaded
from Data Bus
X = Don’t care.
means rising edge triggered.
DAC7800, 7801, 7802
6
SBAS005A
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