DAC7802
BLOCK DIAGRAM
V
DD
21
12
DAC7802
CK
DAC A Register
12
CS A
5
DAC A
2
3
4
22
23
CS B
WR
20
19
DAC B
12
CK
DAC B Register
12
12
DGND
18
6
24
1
I
OUT A
R
FB A
V
REF A
V
REF B
R
FB B
I
OUT B
AGND
PIN CONFIGURATION
Top View
DIP
AGND
I
OUT A
R
FB A
V
REF A
CS A
(LSB) DB0
DB1
DB2
DB3
DB4
DB5
DGND
1
2
3
4
5
6
DAC7802
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
I
OUT B
R
FB B
V
REF B
V
DD
CS B
WR
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB11–DB0
TIMING CHARACTERISTICS
At V
DD
= +5V, and T
A
= –40
o
C to +85
o
C.
t
1
DATA
t
2
5V
0V
PARAMETER
t
1
t
2
t
3
t
4
t
5
-
-
-
-
-
Data Setup Time
Data Hold Time
Chip Select to Write Setup Time
Chip Select to Write Hold Time
Write Pulse Width
MINIMUM
20ns
15ns
30ns
0ns
30ns
CSA, CSB
t
3
t
5
WR
t
4
5V
5V
NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. t
R
= t
R
= 5ns. (2) Timing measurement reference level
V
IH
+ V
IL
is
.
2
LOGIC TRUTH TABLE
CSA
X
1
CSB
X
1
WR
1
X
0
0
1
0
1
0
0
FUNCTION
No Data Transfer
No Data Transfer
A Rising Edge on CSA or CSB Loads
Data to the Respective DAC
DAC A Register Loaded from Data Bus
DAC B Register Loaded from Data Bus
DAC A and DAC B Registers Loaded
from Data Bus
means rising edge triggered.
X = Don’t care.
6
DAC7800, 7801, 7802
www.ti.com
SBAS005A
TI [ TEXAS INSTRUMENTS ]
