INPUT
DAC
A1
A0
R/W
CS
RST
RSTSEL LOADDACS
REGISTER
REGISTER
MODE
DAC
L
L
H
H
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
↑
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
↑
Write
Write
Write
Write
Read
Read
Read
Read
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Write
Write Input
Write Input
Write Input
Write Input
Read Input
Read Input
Read Input
Read Input
Update
A
B
C
D
A
B
C
D
All
All
All
All
L
H
H
H
H
X
X
X
X
L
H
L
H
H
X
X
X
X
H
X
X
X
X
H
X
X
Hold
Hold
Reset to Zero
Reset to Midscale
Hold
Reset to Zero
Reset to Midscale
↑
H
TABLE I. DAC7744 Logic Truth Table.
DIGITALLY-PROGRAMMABLE
CURRENT SOURCE
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7744. Note
that each DAC register is edge triggered and not level
triggered. When the LOADDACS signal is transitioned to
HIGH, the digital word currently in the DAC register is
latched. The first set of registers (the input registers) are
triggered via the A0, A1, R/W, and CS inputs. Only one of
these registers is transparent at any given time.
The DAC7744 offers a unique set of features that allows a
wide range of flexibility in designing applications circuits
such as programmable current sources. The DAC7744 offers
both a differential reference input as well as an open-loop
configuration around the output amplifier. The open-loop
configuration around the output amplifier allows transistor
to be placed within the loop to implement a digitally-
programmable, uni-directional current source. The availabil-
ity of a differential reference also allows programmability
for both the full-scale and zero-scale currents. The output
current is calculated as:
The double-buffered architecture is designed mainly so that
each DAC input register can be written to at any time and
then all DAC voltages updated simultaneously by the rising
edge of LOADDACS. It also allows a DAC input register to
be written to at any point then the DAC output voltages can
be synchronously changed via a trigger signal connected to
LOADDACS.
VREFH – VREF
RSENSE
L
N
IOUT
=
•
(2)
65,536
DIGITAL TIMING
+ VREFL / RSENSE
(
)
Figure 11 and Table II provide detailed timing for the digital
interface of the DAC7744.
Figure 12 shows a DAC7744 in a 4-to-20mA current output
configuration. The output current can be determined by
Equation 3:
DIGITAL INPUT CODING
The DAC7744 input data is in Straight Binary format. The
output voltage is given by Equation 1.
(3)
5V –1V
N
1V
IOUT
=
•
+
V
REFH – VREFL • N
(
)
(1)
250Ω
65,536
250Ω
VOUT = VREFL +
65,536
where N is the digital input code. This equation does not
include the effects of offset (zero scale) or gain (full scale)
errors.
At full scale, the output current is 16mA plus the 4mA for
the zero current. At zero scale, the output current is the offset
current of 4mA (1V/250Ω).
®
21
DAC7744
TI [ TEXAS INSTRUMENTS ]
