by the external voltage references (VREFL and VREFH, re-
spectively). The digital input is a 16-bit parallel word and
the DAC input registers offer a readback capability. The
converters can be powered from either a single +15V supply
or a dual ±15V supply. The device offers a reset function
which immediately sets all DAC output voltages and DAC
registers to mid-scale code 8000H or to zero scale, code
0000H. See Figures 2 and 3 for the basic operation of the
DAC7744.
THEORY OF OPERATION
The DAC7744 is a quad voltage output, 16-bit digital-to-
analog converter (DAC). The architecture is an R-2R ladder
configuration with the three MSB’s segmented followed by
an operational amplifier that serves as a buffer. Each DAC
has its own R-2R ladder network, segmented MSBs and
output op amp (see Figure 1). The minimum voltage output
(zero scale) and maximum voltage output (full scale) are set
RF
VOUT Sense
VOUT
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREF
VREFH Sense
VREF
VREFL Sense
H
L
FIGURE 1. DAC7744 Architecture.
1
2
3
4
5
6
7
8
9
DB15 (MSB)
DB14
DB13
DB12
DB11
DB10
DB9
NC 48
NC 47
NC 46
NC 45
VOUTA Sense 44
0V to +10V
+10.000V
VOUT
VREFL AB Sense 42
REFL AB 41
A
43
DB8
V
Data
Bus
DB7
VREFH AB 40
VREFH AB Sense 39
VOUTB Sense 38
10 DB6
11 DB5
0V to +10V
0V to +10V
+10.000V
12 DB4
VOUT
VOUTC Sense 36
VOUT
35
B
37
DAC7744
13 DB3
14 DB2
C
15 DB1
VREFH CD Sense 34
VREFH CD 33
16 DB0 (LSB)
17 RSTSEL
18 RST
19 LOADDACS
20 R/W
VREFL CD 32
Reset DACs
Load DAC Registers
READ/WRITE
VREFL CD Sense 31
VOUTD Sense 30
0V to +10V
VOUTD
29
21 A1
VSS 28
AGND 27
VCC 26
Address
22 A0
+15V
Chip Select
23 CS
+
+
0.1µF
0.1µF
1µF
24 DGND
VDD 25
NC = No Connection
+5V
1µF
FIGURE 2. Basic Single-Supply Operation of the DAC7744.
®
16
DAC7744