TIMING CHARACTERISTICS
V
CC
= +15V, V
SS
= –15V, V
DD
= 5V; R
L
= 2kΩ to AGND; C
L
= 200pF to AGND; all specifications –40°C to +85°C, unless otherwise noted.
DAC7731
PARAMETER
t
WH
t
WL
t
SDI
t
HDI
t
SCS
t
HSC
t
DDO
t
HDO
t
DDOZ
t
WCSH
t
WLDL
t
WLDH
t
SLD
t
DLD
t
SCLK
t
SRS
t
HRS
t
WRL
t
S
DESCRIPTION
SCLK HIGH Time
SCLK LOW Time
Setup Time: Data in valid before rising SCLK
Hold Time: Data in valid after rising SCLK
Setup Time: CS falling edge before first rising SCLK
Hold Time: CS rising edge after 16th rising SCLK
Delay Time: CS Falling Edge to Data Out valid, C
L
= 20pF on SDO
Hold Time: Data Out valid after SCLK rising edge, C
L
20pF on SDO
Delay Time: CS rising edge to SDO = High Impedance
CS HIGH Time
LDAC LOW Time
LDAC HIGH Time
Setup Time: 16th Rising SCLK Before LDAC Rising Edge
Delay Time: LDAC rising edge to first SCLK rising edge of next
transfer cycle.
Setup Time: CS High before falling SCLK edge following 16th
rising SCLK edge
Setup Time: RSTSEL Valid Before RST LOW
Hold Time: RSTSEL valid after RST HIGH
RST LOW Time
DAC V
OUT
Settling Time
MIN
25
25
5
20
15
0
50
50
70
50
20
20
15
15
5
0
20
30
5
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
INTERFACE TIMING
t
SCS
CS
t
WH
SCLK
t
SDI
SDI
t
DDO
t
HDO
SDO
A15
A14
A13
B15
1
2
t
HDI
B14
B13
t
WL
16
t
SCLK
t
HCS
t
WCSH
B0
C15
C14
C13
C12
Word B
t
DDOZ
A0
t
DLD
Word A
t
WLDL
t
WLDH
t
SLD
t
S
B15
Word C
B14
B13
B12
Word B
LDAC
V
OUT
±0.003%
of FSR
Error Bands
RESET TIMING
t
SRS
RSTSEL
t
HRS
RST
+FS
V
OUT
(RSTSEL = LOW)
–FS
+FS
V
OUT
(RSTSEL = HIGH)
–FS
Mid-Scale
t
WRL
t
S
Min-Scale
4
DAC7731
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SBAS249B
TI [ TEXAS INSTRUMENTS ]
