DIGITAL TIMING
DIGITAL INPUT CODING
Figure 3 and Table II provide detailed timing for the digital
interface of the DAC7624 and DAC7625.
The DAC7624 and DAC7625 input data is in straight binary
format. The output voltage is given by the following equa-
tion:
V
– VREFL • N
(
+
)
REFH
VOUT = VREFL
4096
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
tWCS
CS
tWS
tWH
R/W
tRCS
tAH
CS
tAS
tRDH
tRDS
A0/A1
R/W
tLWD
tLH
tLS
tAS
tAH
LDAC
A0/A1
tDH
tDS
tDZ
Data In
Data Out
Data Valid
tCSD
tRESET
RESET
Data Output Timing
Digital Input Timing
FIGURE 3. Digital Input and Output Timing.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tRCS
tRDS
tRDH
tDZ
tCSD
tWCS
tWS
tWH
tAS
tAH
tLS
tLH
tDS
tDH
tLWD
tRESET
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
CS HIGH to Data Bus in High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
200
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
100
160
50
0
0
0
0
70
50
0
0
50
50
R/W LOW to CS LOW
R/W LOW after CS HIGH
Address Valid to CS LOW
Address Valid after CS HIGH
LDAC LOW to CS LOW
LDAC LOW after CS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LDAC LOW
RESET LOW
TABLE II. Timing Specifications (TA = –40°C to +85°C).
®
11
DAC7624/7625
TI [ TEXAS INSTRUMENTS ]
