DAC712
SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
.................................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
(1)
LINEARITY ERROR MAX
AT +25°C
±4LSB
±4LSB
±2LSB
±2LSB
±2LSB
±2LSB
±2LSB
±2LSB
DIFFERENTIAL
LINEARITY ERROR MAX
AT +25°C
±4LSB
±4LSB
±2LSB
±2LSB
±2LSB
±2LSB
±1LSB
±1LSB
PACKAGE-
LEAD
PDIP-28
SOIC-28
PDIP-28
SOIC-28
PDIP-28
SOIC-28
PDIP-28
SOIC-28
PACKAGE
DESIGNATOR
NT
DW
NT
DW
NT
DW
NT
DW
SPECIFIED
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PRODUCT
DAC712P
DAC712U
DAC712PB
DAC712UB
DAC712PK
DAC712UK
DAC712PL
DAC712UL
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at
www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
DAC712
+V
CC
to COMMON
–V
CC
to COMMON
+V
CC
to –V
CC
Digital Inputs to COMMON
External Voltage Applied to BPO and Range Resistors
V
REF
V
OUT
Power Dissipation
Storage Temperature Range
(1)
OUT
UNIT
V
V
V
V
V
0, +17
0, –17
34
–1 to +V
CC
– 0.7
±V
CC
Indefinite Short to COMMON
Indefinite Short to COMMON
750
–60 to +150
mW
°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
TRUTH TABLE
A
0
A
1
WR
1
→
0
→
1
1
→
0
→
1
1
→
0
→
1
0
1
X
CLR
1
1
1
1
1
0
DESCRIPTION
Load Input Latch
Load D/A Latch
No Change
Latches Transparent
No Change
Reset D/A Latch
0
1
1
0
X
X
1
0
1
0
X
X
2
Submit Documentation Feedback
Product Folder Link(s):
DAC712
Copyright © 2000–2009, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
