DAC712
www.ti.com ................................................................................................................................................. SBAS023A–SEPTEMBER 2000–REVISED JULY 2009
Internal
+10V Reference
VREF OUT
5
10kW
+10V
R1
R2
170W
250W
340W
500W
10kW
Gain Adjust(1)
-10V
(2)
6
4
Bipolar Offset Adjust(1)
5kW
15kW
9.75kW
10kW
R3
R4
20kW
10kW
RFB VREF A
0V to 10V
(3)
3
IDAC
0mA-2mA
±10V VOUT
0V to +10V
DAC712
RFB VREF B
(4)
(1) For no external adjustments, pins 4 and 6 are not connected. External Resistors R1 to R4 tolerance is ±1% values. Range of adjustment
is at least ±0.3% FSR.
(2) Suggested op amps: OPA177GP, GS or OPA604AP, AU.
(3) Suggested op amps: single OPA177GP, GS or dual OPA2604AP, AU.
(4) Suggested D/A converters: dual DAC7800 (serial input, 12-bit resolution); dual DAC7801 (8-bit port input, 12-bit resolution); dual
DAC7802 (12-bit port input, 12-bit resolution); dual DAC7545 (12-bit port input, 12-bit resolution); or single DAC8043 (serial input, 12-bit
resolution). BIPOLAR (complete): DAC813 (use 11-bit resolution for 0V to +10V output; no op-amps required).
Figure 14. Gain and Offset Adjustment Using D/A Converters
DIGITAL INTERFACE
BUS INTERFACE
SINGLE-BUFFERED OPERATION
The DAC712 has 16-bit, double-buffered data bus
interface with control lines for easy interface to
interface to a 16-bit bus. The double-buffered feature
permits update of several D/A converters
simultaneously.
To operate the DAC712 interface as a single-buffered
latch, the DATA INPUT LATCH is permanently
A0
A1
enabled by connecting
to DCOM. If
is not used
to enable the D/A converter, it should be connected
to DCOM as well. For this mode of operation, the
width of WR must be at least 80ns minimum to pass
data through the DATA INPUT LATCH and into the
D/A LATCH.
A0
is the enable control for the DATA INPUT LATCH.
A1
is the enable for the D/A LATCH. WR is used to
A0
A1
strobe data into latches enabled by
and . Refer
to the block diagram of Figure 8 and to Figure 1.
TRANSPARENT INTERFACE
CLR sets the INPUT DATA LATCH to all zeros and
the D/A LATCH to a code that gives bipolar 0V at the
D/A converter output.
The digital interface of the DAC712 can be made
A0 A1
transparent by asserting
asserting CLR HIGH.
,
, and WR LOW, and
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