DAC712
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SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
ELECTRICAL CHARACTERISTICS: DAC712P, U, PB, UB
At T
A
= +25°C, +V
CC
= +12V and +15V, and –V
CC
= –12V and –15V, unless otherwise noted.
PARAMETER
INPUT
RESOLUTION
Resolution
DIGITAL INPUTS
Input Code
Logic Levels
(2)
V
IH
V
IL
I
IH
(V
I
= +2.7V)
I
IL
(V
I
= +0.4V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
T
MIN
to T
MAX
Differential Linearity Error
T
MIN
to T
MAX
Monotonicity Over Temperature
Gain Error
(3)
T
MIN
to T
MAX
Bipolar Zero Error
(3)
T
MIN
to T
MAX
13
±0.1
±0.2
±0.1
±20
±0.2
±40
Power-Supply Sensitivity of Full-Scale
DYNAMIC PERFORMANCE
Settling Time (to ±0.003%FSR, 5kΩ || 500pF Load)
(5)
20V Output Step
1LSB Output Step
Output Slew Rate
Total Harmonic Distortion + Noise
0dB, 1001Hz, f
S
= 100kHz
–20dB, 1001Hz, f
S
= 100kHz
–60dB, 1001Hz, f
S
= 100kHz
SINAD
1001Hz, f
S
= 100kHz
Digital Feedthrough
(6)
Digital-to-Analog Glitch Impulse
(6)
(6)
TEST
CONDITIONS
DAC712P, U
MIN
TYP
MAX
DAC712PB, UB
(1)
MIN
TYP
MAX
UNIT
16
Binary Twos Complement
+2.0
0
+V
CC
– 1.4
+0.8
±10
±10
Bits
V
V
µA
µA
±4
±8
±4
±8
14
±2
±4
±2
±4
LSB
LSB
LSB
LSB
Bits
%
±0.15
%
% FSR
(4)
mV
±0.15
±30
% FSR
mV
% FSR/% V
CC
ppm FSR/% V
CC
±0.003
±30
6
4
10
0.005
0.03
3.0
87
2
15
120
10
µs
µs
V/µs
%
%
%
dB
nV-s
nV-s
nV/√Hz
Output Noise Voltage (Includes Reference)
(1)
(2)
(3)
(4)
(5)
(6)
Shaded cells indicate same specification as the DAC712P, U grade.
Digital inputs are TTL- and +5V CMOS-compatible over the specified temperature range.
Errors externally adjustable to zero.
FSR means Full-Scale Range. For example, for a ±10V output, FSR = 20V.
Maximum represents the 3σ limit. Not 100% tested for this parameter.
For the worst-case code changes: FFFFh to 0000h and 0000h to FFFFh. These are binary twos complement (BTC) codes.
Copyright © 2000–2009, Texas Instruments Incorporated
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