CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACE
SCAS647D − OCTOBER 2000 − REVISED APRIL 2013
V
O
= 3.3 V
R = 1 kΩ
L
DUT
C = 10 pF
L
GND
TEST CIRCUIT
4 to N Bytes for Complete Device Programming
Bit 0
Start
Condition
(S)
Stop
Condition
(P)
Bit 7
MSB
Acknowledge
(A)
LSB
Bit 6
(R/W)
t
t
su(START)
t
w(SCLL)
w(SCLH)
0.7 V
0.3 V
CC
SCLOCK
CC
t
t
r
su(START)
t
PHL
t
t
f
(BUS)
t
PLH
0.7 V
0.3 V
CC
SDATA
CC
t
t
f(SDATA)
r(SDATA)
t
t
su(STOP)
h(SDATA)
t
t
su(SDATA)
h(START)
Repeat Start
Stop Condition
Condition
Start or Repeat Start
Condition
(see Note A)
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
Slave Address
1
2
3
Common (Dummy Value, Ignored)
Byte Count = N
4
Data Byte 0
5 − N
Data Byte 1 − N
NOTE A: The repeat start condition is supported. If PWRDWN# is asserted SDATA will be set to off-state, high impedance.
Figure 10. Propagation Delay Times, t and t
r
f
13
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TI [ TEXAS INSTRUMENTS ]
