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CDCE706PWG4 参数 Datasheet PDF下载

CDCE706PWG4图片预览
型号: CDCE706PWG4
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程3 -PLL时钟合成器/乘法器/除法器 [PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER]
分类和应用: 晶体时钟发生器微控制器和处理器外围集成电路光电二极管信息通信管理
文件页数/大小: 40 页 / 1007 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CDCE706  
SCAS815IOCTOBER 2005REVISED NOVEMBER 2008........................................................................................................................................... www.ti.com  
RECOMMENDED CRYSTAL SPECIFICATIONS  
MIN NOM  
MAX  
54  
UNIT  
MHz  
fXtal  
ESR Effective series resistance(1)(2)  
CIN Input capacitance CLK_IN0 and CLK_IN1  
Crystal input frequency range (fundamental mode)  
8
27  
15  
60  
3
pF  
(1) For crystal frequencies above 50 MHz, the effective series resistor should not exceed 50 to assure stable start-up condition.  
(2) For maximum power handling (drive level), see Figure 15.  
EEPROM SPECIFICATION  
MIN  
100  
10  
TYP  
MAX  
UNIT  
Cycles  
Years  
EEcyc  
EEret  
Programming cycles of EEPROM  
Data retention  
1000  
TIMING REQUIREMENTS  
over recommended ranges of supply voltage, load, and operating-free air temperature  
MIN NOM MAX UNIT  
CLK_IN REQUIREMENTS  
PLL mode  
1
0
200  
200  
4
fCLK_IN  
CLK_IN clock input frequency (LVCMOS or differential)  
MHz  
ns  
PLL bypass mode  
tr/tf  
Rise and fall time, CLK_IN signal (20% to 80%)  
Duty cycle, CLK_IN at VCC/2  
dutyREF  
40%  
60%  
SMBus TIMING REQUIREMENTS (see Figure 11)  
fSCLK  
SCLK frequency  
100  
50  
kHz  
µs  
µs  
µs  
µs  
µs  
µs  
th(START)  
tw(SCLL)  
tw(SCLH)  
tsu(START)  
th(SDATA)  
tsu(SDATA)  
START hold time  
4
4.7  
4
SCLK low-pulse duration  
SCLK high-pulse duration  
START setup time  
SDATA hold time  
0.6  
0.3  
0.25  
SDATA setup time  
tr(SDATA)  
tr(SM)  
/
SCLK/SDATA input rise time  
SCLK/SDATA input fall time  
1000  
300  
ns  
ns  
tf(SDATA)  
/
tf(SM)  
tsu(STOP)  
t(BUS)  
STOP setup time  
Bus free time  
4
µs  
µs  
4.7  
t(POR)  
Time in which the device must be operational after power-on reset  
500  
ms  
DEVICE CHARACTERISTICS  
over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1  
PARAMETER  
OVERALL PARAMETER  
TEST CONDITIONS  
MIN  
TYP(1)  
MAX UNIT  
All PLLs on, all outputs on,  
fOUT = 80 MHz, fCLK_IN = 27 MHz,  
fVCO = 160 MHz  
ICC  
Supply current(2)  
90  
115  
mA  
Every circuit powered down except SMBus,  
fIN = 0 MHz, VCC = 3.6 V  
ICCPD Power-down current  
50  
µA  
Supply voltage VCC threshold for power-up  
control circuit  
VPUC  
2.1  
V
(1) All typical values are at nominal VCC  
.
(2) For calculating total supply current, add the current from Figure 2, Figure 3, and Figure 4. Using the high-speed mode of the VCO  
reduces the current consumption. See Figure 3.  
6
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