’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Functional Diagram of ’HC4053, CD74HCT4053
IN/OUT
BINARY TO
1 OF 2
DECODERS
WITH ENABLE
V
CC
C
C
B
B
A
A
0
1
0
1
0
1
LOGIC LEVEL
CONVERSION
16
3
5
1
2
13
12
TG
TG
TG
TG
TG
TG
A COMMON
OUT/IN
14
15
S
S
11
10
0
1
B COMMON
OUT/IN
S
9
6
2
C COMMON
OUT/IN
4
E
8
7
GND
V
EE
TRUTH TABLE
’HC4053, CD74HCT4053
INPUT STATES
“ON”
ENABLE
S
S
S
2
CHANNELS
C0, B0, A0
C0, B0, A1
C0, B1, A0
C0, B1, A1
C1, B0, A0
C1, B0, A1
C1, B1, A0
C1, B1, A1
None
0
1
L
L
L
L
L
H
L
L
H
H
L
L
L
L
L
H
L
L
L
H
H
H
H
X
L
H
L
L
L
H
H
X
L
H
X
H
X = Don’t care
5