CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564
Test Circuits and Waveforms
t
r
C
L
CLOCK
90%
10%
t
f
C
L
I
t
WL
+ t
WH
=
fC
L
V
CC
50%
10%
t
WL
50%
50%
GND
t
WH
CLOCK
t
r
C
L
= 6ns
t
WL
+ t
WH
=
t
f
C
L
= 6ns
2.7V
0.3V
I
fC
L
3V
1.3V
0.3V
t
WL
1.3V
1.3V
GND
t
WH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t
r
= 6ns
INPUT
90%
50%
10%
t
f
= 6ns
V
CC
t
r
= 6ns
INPUT
GND
2.7V
1.3V
0.3V
t
f
= 6ns
3V
GND
t
TLH
90%
t
THL
t
TLH
90%
50%
10%
t
PHL
t
PLH
t
THL
INVERTING
OUTPUT
INVERTING
OUTPUT
t
PHL
t
PLH
1.3V
10%
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t
r
C
L
CLOCK
INPUT
90%
10%
t
H(H)
t
f
C
L
V
CC
50%
GND
t
H(L)
V
CC
DATA
INPUT
t
SU(H)
CLOCK
INPUT
t
r
C
L
2.7V
0.3V
t
H(H)
t
f
C
L
3V
1.3V
GND
t
H(L)
3V
1.3V
1.3V
1.3V
t
SU(L)
t
TLH
t
THL
90%
1.3V
10%
t
PHL
GND
DATA
INPUT
t
SU(H)
t
TLH
90%
OUTPUT
t
PLH
t
REM
V
CC
SET, RESET
OR PRESET
50%
t
SU(L)
t
THL
90%
50%
10%
t
PHL
50%
GND
OUTPUT
90%
1.3V
t
PLH
GND
t
REM
3V
SET, RESET
OR PRESET
1.3V
GND
IC
C
L
50pF
IC
C
L
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
TI [ TEXAS INSTRUMENTS ]
