欢迎访问ic37.com |
会员登录 免费注册
发布采购

CD4541BE 参数 Datasheet PDF下载

CD4541BE图片预览
型号: CD4541BE
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS可编程定时器高电压型( 20V额定值) [CMOS PROGRAMMABLE TIMER HIGH VOLTAGE TYPES(20V RATING)]
分类和应用: 计数器光电二极管高压
文件页数/大小: 9 页 / 95 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号CD4541BE的Datasheet PDF文件第2页浏览型号CD4541BE的Datasheet PDF文件第3页浏览型号CD4541BE的Datasheet PDF文件第4页浏览型号CD4541BE的Datasheet PDF文件第5页浏览型号CD4541BE的Datasheet PDF文件第6页浏览型号CD4541BE的Datasheet PDF文件第7页浏览型号CD4541BE的Datasheet PDF文件第8页浏览型号CD4541BE的Datasheet PDF文件第9页  
CD4541B
Data sheet acquired from Harris Semiconductor
SCHS085
CMOS Programmable Timer
High Voltage Types (20V Rating)
Description
CD4541B programmable timer consists of a 16-stage binary
counter, an oscillator that is controlled by external R-C compo-
nents (2 resistors and a capacitor), an automatic power-on
reset circuit, and output control logic. The counter increments
on positive-edge clock transitions and can also be reset via the
MASTER RESET input.
The output from this timer is the Q or Q output from the 8th,
10th, 13th, or 16th counter stage. The desired stage is chosen
using time-select inputs A and B (see Frequency Select Table).
The output is available in either of two modes selectable via the
MODE input, pin 10 (see Truth Table). When this MODE input is
a logic “1”, the output will be a continuous square wave having
a frequency equal to the oscillator frequency divided by 2
N
.
With the MODE input set to logic “0” and after a MASTER
RESET is initiated, the output (assuming Q output has been
selected) changes from a low to a high state after 2
N-1
counts
and remains in that state until another MASTER RESET pulse
is applied or the MODE input is set to a logic “1”.
Timing is initialized by setting the AUTO RESET input (pin 5) to
logic “0” and turning power on. If pin 5 is set to logic “1”, the
AUTO RESET circuit is disabled and counting will not start until
after a positive MASTER RESET pulse is applied and returns
to a low level. The AUTO RESET consumes an appreciable
amount of power and should not be used if low-power operation
is desired. For reliable automatic power-on reset, V
DD
should
be greater than 5V.
The RC oscillator, shown in Figure 2, oscillates with a
frequency determined by the RC network and is calculated
using:
1
-
f =
----------------------------------
2.3 R
TC
C
TC
Where f is between 1kHz
and 100kHz
and R
S
10k
and
2R
TC
Features
• Low Symmetrical Output Resistance, Typically 100Ω
at V
DD
= 15V
• Built-In Low-Power RC Oscillator
• Oscillator Frequency Range . . . . . . . . . . DC to 100kHz
• External Clock (Applied to Pin 3) can be Used Instead
of Oscillator
• Operates as 2
N
Frequency Divider or as a Single-
Transition Timer
• Q/Q Select Provides Output Logic Level Flexibility
• AUTO or MASTER RESET Disables Oscillator During
Reset to Reduce Power Dissipation
• Operates With Very Slow Clock Rise and Fall Times
• Capable of Driving Six Low Power TTL Loads, Three
Low-Power Schottky Loads, or Six HTL Loads Over
the Rated Temperature Range
• Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices”
[ /Title
(CD45
41B)
/Sub-
ject
(CMO
S Pro-
gram-
mable
Timer
High
Volt-
age
Types
(20V
Rat-
ing))
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
CD400
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,
mili-
tary,
mil
Ordering Information
PART NUMBER
CD4541BF
CD4541BE
CD4541BH
CD4541BM
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld PDIP
Chip
14 Ld SOIC
PKG.
NO.
F14.3
E14.3
-
M14.15
Pinout
CD4541B (CERDIP, PDIP, SOIC)
TOP VIEW
R
TC
1
C
TC
2
R
S
3
NC 4
AUTO RESET 5
MASTER RESET 6
V
SS
7
14 V
DD
13 B
12 A
11 NC
10 MODE
9 Q/Q SELECT
8 OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1998
File Number
1378.1
1