CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
VDD
Inputs
VDD
I
VSS
VSS
92CS-27555
Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.
Figure 16. Input Leakage-Current Test Circuit
10
10
Clock
Reset
14
15
1
Q1 Q2
5
4
1
2
3
J2
7
J3
9
J4
12
J5
13
External
Reset
Clock
14
15
1
P E J1
2
3
J2
7
J3
9
J4
12
J5
P E J1
CD4018B
CD4018B
Q1 Q2
5
4
1/4 CD4066B
2
1
3
2
3
1/3 CD4049B
5
4
2
5
6
8
9
12
11
13
Signal
Inputs
12
11
2
1/6 CD4049B
5
3
9
4
11
10
10 kΩ
1
4
12
6
5
13
12
CD4001B
4
9
7
1/3 CD4049B
10
6
13
12
9
8
6
5
2
1
CD4001B
11
10
4
3
10
6
5
11
2
Signal
Outputs
LPF
10 k
Ω
Channel 1
Channel 1
Channel 2
Channel 3
Channel 4
1
4
8
CD4066B
3
LPF
10 kΩ
Channel 2
1/4 CD4066B
3
8
11
CD4066B
9
Package Count
2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B
LPF
10 kΩ
Channel 3
Maximum
Allowable
Signal Level
Clock
VDD
30% (VDD – VSS)
VSS
Chan 1 Chan 2 Chan 3 Chan 4
10
LPF Channel 4
10 kΩ
92CM-30928
Figure 17. Four-Channel PAM Multiplex System Diagram
10
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•
DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
