CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
electrical characteristics
LIMITS AT INDICATED TEMPERATURES
PARAMETER
TEST CONDITIONS
VIN
(V)
0, 5
IDD
Quiescent device
current
0, 10
0, 15
0, 20
Signal Inputs (Vis) and Outputs (Vos)
VC = VDD,
kΩ
RL = 10 k returned
V
DD
*
V
SS
to
,
2
Vis = VSS to VDD
On-state resistance
difference between
any two switches
Total harmonic
distortion
–3-dB cutoff
frequency
(switch on)
–50-dB feedthrough
frequency (switch off)
Iis
Input/output leakage
current (switch off)
(max)
–50-dB crosstalk
frequency
5
10
15
5
RL = 10 kΩ, VC = VDD
k
10
15
VC = VDD = 5 V, VSS = –5 V,
Vis(p-p) = 5 V (sine wave centered on 0 V),
RL = 10 kΩ, fis = 1-kHz sine wave
VC = VDD = 5 V, VSS = –5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ
VC = VSS = –5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ
VC = 0 V, Vis = 18 V, Vos = 0 V;
and
VC = 0 V, Vis = 0 V, Vos = 18 V
VC(A) = VDD = 5 V,
VC(B) = VSS = –5 V,
Vis(A) = 5 Vp-p, 50-Ω source,
RL = 1 kΩ
RL = 200 kΩ, VC = VDD,
VSS = GND, CL = 50 pF,
Vis = 10 V
(square wave centered on 5 V),
tr, tf = 20 ns
VDD = 5 V, VC = VSS = –5 V
VDD = 5 V, VC = VSS = –5 V
VDD = 5 V, VC = VSS = –5 V
18
±0.1
±0.1
±1
±1
800
310
200
850
330
210
1200
500
300
1300
550
320
470
180
125
15
10
5
0.4
%
Ω
1050
400
240
Ω
VDD
(V)
5
10
15
20
–55°C
0.25
0.5
1
5
–40°C
0.25
0.5
1
5
85°C
7.5
15
30
150
125°C
7.5
15
30
150
25°C
TYP
0.01
0.01
0.01
0.02
MAX
0.25
0.5
1
5
µA
A
UNIT
ron
On-state resistance
(max)
∆r
on
r
THD
40
MHz
1
±10
–5
±0.1
MHz
µA
8
MHz
5
10
15
20
10
7
8
8
0.5
40
20
15
pF
pF
pF
ns
tpd
Propagation delay
(signal input to
signal output)
Input capacitance
Output capacitance
Feedthrough
Cis
Cos
Cios
4
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•
DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
