CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
V
DD
Inputs
V
DD
I
V
SS
92CS-27555
V
SS
Measure inputs sequentially to both V
and V . Connect all unused inputs to either V
SS DD
or V . Measure control inputs only.
SS
DD
Figure 16. Input Leakage-Current Test Circuit
10
2
3
7
9
12
10
2
3
7
9
12
Clock
14
15
Clock
Reset
P
J
J
J
J
J
5
E
1
2
3
4
14
15
1
P
J
J
J
J
J
5
E
1
2
3
4
External
Reset
CD4018B
CD4018B
13
Q
1
Q
2
1
Q
5
Q
4
1
2
5
4
1
1/4 CD4066B
2
13
12
9
8
6
5
2
1
1
3
4
7
6
2
1/3 CD4049B
3
5
6
2
4
CD4001B
9
10
1/3 CD4049B
3
10
4
11
5
8
9
10
Signal
Outputs
12
6
5
11
2
5
13
6
12
13
11
12
Channel 1
Channel 2
Channel 3
Channel 4
LPF
11
12
Signal
Inputs
10 kΩ
Channel 1
Channel 2
Channel 3
Channel 4
1/6 CD4049B
5
2
3
1
4
1
4
CD4066B
3
9
LPF
8
9
10 kΩ
CD4066B
1/4 CD4066B
4
3
8
10
11
11
LPF
Package Count
2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B
10 kΩ
10 kΩ
LPF
V
10
DD
Clock
Maximum
Allowable
10 kΩ
30% (V
– V
)
SS
DD
V
SS
Signal Level
Chan 1 Chan 2 Chan 3 Chan 4
92CM-30928
Figure 17. Four-Channel PAM Multiplex System Diagram
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
