CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
description/ordering information (continued)
ORDERING INFORMATION
TA
CDIP − F
PDIP − E
PACKAGE†
Tube of 25
Tube of 25
Tube of 50
−55°C to 125°C
SOIC − M
SOP − NS
TSSOP − PW
Reel of 2500
Reel of 250
Reel of 2000
Tube of 90
Reel of 2000
ORDERABLE
PART NUMBER
CD4066BF3A
CD4066BE
CD4066BM
CD4066BM96
CD4066BMT
CD4066BNSR
CD4066BPW
CD4066BPWR
CD4066B
CM066B
CD4066BM
TOP-SIDE
MARKING
CD4066BF3A
CD4066BE
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Switch
Control
In
Vis
p
n
p
n
Out
Vos
Control
VC†
n
VSS
VDD
VSS
† All control inputs are protected by the CMOS protection network.
NOTES: A. All p substrates are connected to VDD.
B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS
C. Signal-level range: VSS
≤
Vis
≤
VDD
92CS-29113
Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265