CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms (Continued)
V
V
V
DD
DD
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
I
DD
I
I
DD
DD
CD4052
CD4051
CD4053
FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF
V
DD
V
DD
OUTPUT
OUTPUT
OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
R
C
L
R
V
C
L
L
DD
L
R
C
L
L
V
V
DD
EE
V
EE
V
V
DD
DD
V
EE
V
V
V
EE
EE
V
V
V
DD
EE
V
V
SS
SS
CLOCK
IN
CLOCK
IN
V
SS
CLOCK
IN
V
SS
SS
SS
V
V
CD4051
V
CD4053
SS
SS
CD4052
SS
FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
V
V
DD
DD
OUTPUT
OUTPUT
OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
V
DD
R
50pF
V
R
50pF
L
L
R
L
50pF
14
13
12
11
10
9
V
EE
EE
V
V
EE
V
V
DD
V
DD
DD
DD
V
V
V
DD
SS
DD
V
SS
CLOCK
IN
V
V
V
V
V
CLOCK
IN
V
V
EE
EE
SS
CLOCK
IN
EE
SS
SS
SS
V
V
V
SS
SS
SS
t
AND t
PLH
t
AND t
PLH
t
AND t
PHL
PHL
PHL PLH
CD4052
CD4051
CD4053
FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
V
DD
V
DD
V
DD
µA
1K
V
IH
1
2
3
4
5
6
7
8
16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
1K
1K
15
14
13
12
11
10
9
µA
µA
15
14
13
12
11
10
9
1K
1K
V
V
IH
IH
V
1K
IH
V
IH
V
IL
V
IL
V
V
IL
IL
V
IH
CD4053B
CD4052B
CD4051B
V
IL
V
IL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6)
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 2x)
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL by)
FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
10