CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms
V
= 15V
V
= 7.5V
V
DD
= 5V
V
= 5V
DD
DD
DD
5V
5V
7.5V
16
16
16
16
V
= 0V
V
= 0V
SS
SS
V
= 0V
SS
V
= 0V
= 0V
EE
7
8
7
8
7
8
7
8
V
= -10V
V
= -5V
V
= -7.5V
EE
EE
EE
V
SS
(D)
(C)
(B)
(A)
NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels
are: “0” = V and “1” = V . The analog signal (through the TG) may
SS DD
swing from V to V
.
EE
DD
FIGURE 9. TYPICAL BIAS VOLTAGES
t = 20ns
r
t = 20ns
r
t = 20ns
f
t = 20ns
f
90%
90%
50%
90%
50%
90%
50%
50%
10%
10%
10%
10%
10%
TURN-ON TIME
90%
50%
90%
10%
10%
TURN-OFF TIME
TURN-ON
TIME
TURN-OFF TIME
t
PHZ
FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON
(R = 1kΩ)
FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF
(R = 1kΩ)
L
L
V
V
V
DD
DD
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
I
I
DD
DD
I
DD
CD4053
CD4051
CD4052
FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF
9