CD4051B, CD4052B, CD4053B
Functional Block Diagrams
(Continued)
CD4052B
X CHANNELS IN/OUT
3
11
2
15
1
14
0
12
TG
16 V
DD
TG
TG
TG
A
B
INH
COMMON X
OUT/IN
13
3
COMMON Y
OUT/IN
†
†
†
10
9
6
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
TG
TG
TG
TG
1
0
5
1
2
2
4
3
8 V
SS
7
V
EE
Y CHANNELS IN/OUT
CD4053B
BINARY TO
1 OF 2
DECODERS
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
IN/OUT
cy
3
cx
5
by
1
bx
2
ay
13
ax
12
TG
COMMON
OUT/IN
ax OR ay
14
16 V
DD
A
†
11
TG
COMMON
OUT/IN
bx OR by
15
TG
B
†
10
TG
COMMON
OUT/IN
cx OR cy
4
TG
C
†
9
TG
INH
†
6
V
DD
8
V
SS
7
V
EE
†
All inputs are protected by standard CMOS protection network.
3