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CD4050BEE4 参数 Datasheet PDF下载

CD4050BEE4图片预览
型号: CD4050BEE4
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS六缓冲器转换器 [CMOS Hex Buffer Converters]
分类和应用: 转换器逻辑集成电路光电二极管
文件页数/大小: 38 页 / 1725 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CD4049UB, CD4050B
Data sheet acquired from Harris Semiconductor
SCHS046I
August 1998 - Revised May 2004
CMOS Hex Buffer/Converters
The CD4049UB and CD4050B devices are inverting and
non-inverting hex buffers, respectively, and feature logic-
level conversion using only one supply voltage (V
CC
). The
input-signal high level (V
IH
) can exceed the V
CC
supply
voltage when these devices are used for logic-level
conversions. These devices are intended for use as CMOS
to DTL/TTL converters and can drive directly two DTL/TTL
loads. (V
CC
= 5V, V
OL
0.4V, and I
OL
3.3mA.)
Applications
• CMOS to DTL/TTL Hex Converter
• CMOS Current “Sink” or “Source” Driver
• CMOS High-To-Low Logic Level Converter
[ /Title
(CD40
49UB,
CD405
The CD4049UB and CD4050B are designated as
0B)
replacements for CD4009UB and CD4010B, respectively.
Because the CD4049UB and CD4050B require only one
/Sub-
power supply, they are preferred over the CD4009UB and
ject
CD4010B and should be used in place of the CD4009UB
(CMO
and CD4010B in all inverter, current driver, or logic-level
S Hex
conversion applications. In these applications the
Buffer/
CD4049UB and CD4050B are pin compatible with the
CD4009UB and CD4010B respectively, and can be
Con-
substituted for these devices in existing as well as in new
verters)
designs. Terminal No. 16 is not connected internally on the
/Autho
CD4049UB or CD4050B, therefore, connection to this
terminal is of no consequence to circuit operation. For
r ()
applications not requiring high sink-current or voltage
/Key-
conversion, the CD4069UB Hex Inverter is recommended.
words
(Harris
Features
Semi-
• CD4049UB Inverting
con-
• CD4050B Non-Inverting
ductor,
• High Sink Current for Driving 2 TTL Loads
CD400
• High-To-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20V
0,
• Maximum Input Current of 1µA at 18V Over Full Package
metal
Temperature Range; 100nA at 18V and 25
o
C
gate,
• 5V, 10V and 15V Parametric Ratings
CMOS
Ordering Information
PART NUMBER
CD4049UBF3A
CD4050BF3A
CD4049UBD
CD4049UBDR
CD4049UBDT
CD4049UBDW
CD4049UBDWR
CD4049UBE
CD4049UBNSR
CD4049UBPW
CD4049UBPWR
CD4050BD
CD4050BDR
CD4050UBDT
CD4050BDW
CD4050BDWR
CD4050BE
CD4050NSR
CD4050BPW
CD4050BPWR
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffix R denotes tape
and reel. The suffix T denotes a small-quantity reel of 250.
Pinouts
CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP)
TOP VIEW
V
CC
1
G=A 2
A 3
H=B 4
B 5
I=C 6
C 7
V
SS
8
16 NC
15 L = F
14 F
13 NC
12 K = E
11 E
10 J = D
9 D
CD4050B (PDIP, CERDIP, SOIC, SOP)
TOP VIEW
V
CC
1
G=A 2
A 3
H=B 4
B 5
I=C 6
C 7
V
SS
8
16 NC
15 L = F
14 F
13 NC
12 K = E
11 E
10 J = D
9 D
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright
©
2004, Texas Instruments Incorporated