EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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