CC2510Fx / CC2511Fx
the time between succeeding PM{1 - 3} modes
(i.e. the time in active mode) must be larger
than the startup time for the HS XOSC (see
Table 11 and Table 12) plus the initial
calibration time for the low power RCOSC
(Table 14).
between
setting
SLEEP.MODE≠00
and
asserting PCON.IDLE should be as short as
possible. The SLEEP.MODE will be cleared to
00 by HW when power mode is entered, thus
interrupts are enabled during power modes. All
interrupts not to be used to wake up from
power modes must be disabled before setting
SLEEP.MODE≠00.
12.1.4 Power Management Registers
It should be noted that after enabling the HS
XOSC (CLKCON.OSC=0) one has to ensure
This section describes the Power Management
registers. All register bits retain their previous
values when entering PM2 or PM3 unless
otherwise stated.
that
the
HS
XOSC
before
is
stable
entering
(SLEEP.XOSC_STB=1)
PM{1 - 3}.
If the low power RCOSC is enabled
(CLKCON.OSC32K=1) and the HS XOSC is
selected as clock source for the system clock,
PCON (0x87) - Power Mode Control
Bit
7:2
1
Field Name
Reset
R/W
Description
0
0
0
R/W
Not used
R0/W1 Reserved. Must be set to 0. Failure to do so will stop CPU from operating.
0
IDLE
R0/W1
H0
Power mode control. Writing a 1 to this bit forces CC2510Fx/CC2511Fx to enter the
power mode set by SLEEP.MODE. This bit is always read as 0.
All interrupt requests will clear this bit and CC2510Fx/CC2511Fx will reenter active
mode.
Note: See Section 12.1.3 for details on how this bit should be used.
SWRS055F
Page 75 of 241
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