CC2510Fx / CC2511Fx
Byte
Bit
Field Name
Description
Offset
7
3
IRQMASK
Interrupt Mask for this channel.
0
1
Disable interrupt generation
Enable interrupt generation upon reaching transfer count
7
2
M8
When variable length transfer count is used (VLEN≠000and VLEN≠111) this field
determines whether to use seven or eight bits of the first byte in source data to
determine the transfer count. Only applicable when WORDSIZE=0.
0
1
Use all 8 bits
Use 7 LSB
7
1:0
PRIORITY[1:0]
The DMA channel priority:
00
01
Low, DMA access will always defer to a CPU access
Normal, guarantees that DMA access prevails over CPU on at least every
second try.
10
11
High, DMA access will always prevail over CPU access.
Reserved
Table 52: DMA Configuration Data Structure
12.5.8 DMA Registers
This section describes the SFRs associated
with the DMA Controller.
DMAARM (0xD6) - DMA Channel Arm
Bit
Field Name
Reset
R/W
Description
7
ABORT
0
R0/W
DMA abort. Ongoing byte/word transfers or armed DMA channels will be aborted
when writing a 1 to this bit, and at the same time select which DMA channels to
abort by setting the corresponding, DMAARM.DMAARMnbits to 1
0
1
Normal operation
Abort channels all selected channels
6:5
4
-
R0
Not used
DMAARM4
DMAARM3
DMAARM2
DMAARM1
DMAARM0
0
R/W
DMA arm channel 4
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
3
2
1
0
0
0
0
0
R/W
R/W
R/W
R/W
DMA arm channel 3
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
DMA arm channel 2
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
DMA arm channel 1
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
DMA arm channel 0
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
SWRS055F
Page 106 of 241
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