CC1200
4
Block Diagram
CC120x
4 kbyte
ROM
(optional 40 kHz
clock input)
Ultra low power 40 kHz
auto-calibrated RC oscillator
Power on reset
A system block diagram of
CC1200
is shown Figure 4.1.
RADIO CONTROL &
AES-128
accelerator
MARC
SPI
Main Radio Control unit
Serial configuration
Ultra low power 16 bit
POWER MANAGEMENT
data interface
and
MCU
CSn (chip select)
SI (serial input)
RXFIFO
LNA_P
System bus
ADC
DEMODULATOR
Interrupt and
IO handler
SO (serial output)
LNA
LNA_N
DIGITAL INTERFACE TO MCU
PACKET HANDLER
ADC
eWOR
Enhanced ultra low power
Wake On Radio timer
Battery sensor /
temp sensor
Configuration and
status registers
SCLK
SO (GPIO0)
SI
CS_N
GPIO1
GPIO2
GPIO3
SCLK (serial clock)
0
90
FREQ
SYNTH
256 byte
FIFO RAM
buffer
Packet handler
and FIFO control
(optional GPIO3/2/0)
RF and DSP frontend
PA out
BIAS
XOSC
Q
Fully integrated fractional-N
frequency synthesizer
Modulator
+16 dBm high
efficiency PA
I
TXFIFO
PA
PA
Output power ramping and OOK / ASK modulation
MODULATOR
(optional auto detected
external XOSC / TCXO)
XOSC_Q1
XOSC
XOSC_Q2
Data interface with
signal chain access
RBIAS
LFC0
XOSC_Q1
XOSC_Q2
EXT_XOSC
LFC1
LNA_P
High linearity
LNA
LNA_N
IF amp
90 dB dynamic
range ADC
(optional bit clock)
Channel
filter
Cordic
Highly flexible FSK / OOK
demodulator
(optional low jitter serial
data output for legacy
protocols)
IF amp
90 dB dynamic
range ADC
(optional GPIO for
antenna diversity)
AGC
Automatic Gain Control, 60dB VGA range
RSSI measurements and carrier sense detection
Figure 4.1 : System Block Diagram
4.1
Frequency Synthesizer
At the heart of
CC1200
there is a fully integrated, fractional-N, ultra high performance frequency
synthesizer. The frequency synthesizer is designed for excellent phase noise performance,
providing very high selectivity and blocking performance. The system is designed to comply with
the most stringent regulatory spectral masks at maximum transmit power.
Either a crystal can be connected to XOSC_Q1 and XOSC_Q2, or a TCXO can be connected to
the EXT_XOSC input. The oscillator generates the reference frequency for the synthesizer, as
well as clocks for the ADC and the digital part. To reduce system cost,
CC1200
has high accuracy
frequency estimation and compensation registers to measure and compensate for crystal
inaccuracies, enabling the use of lower cost crystals. If a TCXO is used, the
CC1200
will
automatically turn the TCXO on and off when needed to support low power modes and Wake-On-
Radio operation.
4.2
Receiver
CC1200
features a highly flexible receiver. The received RF signal is amplified by the low-noise
amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At
IF, the I/Q signals are digitized by the high dynamic range ADCs.
An advanced Automatic Gain Control (AGC) unit adjusts the front-end gain, and enables the
CC1200
to receive both strong and weak signals, even in the presence of strong interferers. High
attenuation channel and data filtering enable reception with strong neighbor channel interferers.
The I/Q signal is converted to a phase / magnitude signal to support both FSK and OOK
modulation schemes.
A novel I/Q compensation algorithm removes any problem of I/Q mismatch and hence avoids time
consuming and costly I/Q / image calibration steps in production or in the field.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
SWRS123B – REVISED JUNE 2013
Page 19 of 23
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