CC1110Fx / CC1111Fx
8
Circuit Description
VDD (2.0 - 3.6 V)
ON-CHIP VOLTAGE
REGULATOR
DCOUPL
RESET
WATCHDOG TIMER
RESET_N
DIGITAL
ANALOG
MIXED
POWER ON RESET
XOSC_Q2
XOSC_Q1
HIGH SPEED
CRYSTAL OSC
(24 – 27 MHz)
CLOCK MUX &
CALIBRATION
SLEEP TIMER
P2_4
P2_3
P2_2
P2_1
P2_0
32.768 kHz
CRYSTAL OSC
POWER MGT. CONTROLLER
HIGH SPEED
RC-OSC
DEBUG
INTERFACE
LOW PWR
RC-OSC
1 KB
FIFO SRAM
CC1111Fx
CODE
XDATA
DATA
SFR
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
DP
USB PHY
USB BUS
RAM
USB
8051 CPU
CORE
DM
MEMORY
ARBITRATOR
4 KB
SRAM
32 KB
FLASH
UNIFIED
FLASH
DMA
IRQ
CTRL
FLASH CTRL
CC1110Fx
P0_7
I2S
P0_6
AES
ENCRYPTION &
DECRYPTION
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
RADIO / I2S REGISTERS
RADIO DATA INTERFACE
ADC
AUDIO / DC
AGC DEMODULATOR
MODULATOR
USART 0
USART 1
TIMER 1 (16-bit) + DS Module
RECEIVE
CHAIN
TRANSMIT
CHAIN
TIMER 2 (8-bit MAC Timer)
TIMER 3 (8-bit)
TIMER 4 (8-bit)
RF_P
RF_N
Figure 9:C C1110Fx/CC1111Fx Block Diagram
related to power, test, and clock distribution. In
the following sub-sections, a short description
of each module that appears in Figure 9.
A block diagram of CC1110Fx/CC1111Fx is shown
in Figure 9. The modules can be divided into
one out of three categories: CPU-related
modules, radio-related modules, and modules
SWRS033H
Page 33 of 246
TI [ TEXAS INSTRUMENTS ]
