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BQ24030RHLR 参数 Datasheet PDF下载

BQ24030RHLR图片预览
型号: BQ24030RHLR
PDF下载: 下载PDF文件 查看货源
内容描述: 单片充电和系统电源路径管理IC ( bqTINYTM - III ) [SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC(bqTINYTM-III)]
分类和应用: 电源电路电源管理电路PC
文件页数/大小: 32 页 / 853 K
品牌: TI [ TEXAS INSTRUMENTS ]
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bq24030, bq24031, bq24032,
bq24032A, bq24035, bq24038, bq24039
www.ti.com
SLUS618C – AUGUST 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
over junction temperature range (0°C
T
J
125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
STAT1, STAT2. ACPG AND USBPG, PG OPEN DRAIN (OD)
V
OL
I
LKG
V
IL
V
IH
I
IL
I
IH
I
IL
I
IH
I
IL1
I
IH1
t
(CE-HLDOFF)
PSEL INPUT
V
IL
Low-level input voltage
Falling Hi→Low; 280 K ± 10% applied
when low. (bq24030/2A/5/8)
(bq24032 only)
V
IH
I
IL
I
IH
TIMERS
K
(TMR)
R
(TMR)
(17)
TEST CONDITIONS
OUTPUTS
(16)
MIN
TYP
MAX
UNIT
Low-level output saturation voltage
Input leakage current
I
OL
= 5 mA, An external pullup
resistor
1 K required.
1
0.25
5
V
µA
ISET2, CE, VBSEL, AND ISET3 INPUTS
Low-level input voltage
High-level input voltage
Low-level input current, CE or
ISET3
High-level input current, CE or
ISET3
Low-level input current, ISET2
High-level input current, ISET2
Low-level input current
High-level input current
Holdoff time, CE
V
ISET2
= 0 V
V
ISET2
= V
CC
VBSEL = Low
VBSEL = High
CE going low only
4
5
–20
40
1
15
6
ms
0
1.4
–1
1
µA
0.4
V
0.975
0
V
IL
+ .01
1.4
–1
1
1.025
0.4
V
IL
+ .024
V
High-level input voltage
Low-level input current, PSEL
High-level input current, PSEL
Input R
PSEL
sets external hysteresis
(bq24030/2A/5/8)
(bq24032 only)
V
µA
µA
Timer set factor
External resistor limits
Precharge timer
Timer fault recovery pullup from
OUT to BAT
t
(CHG)
= K
(TMR)
× R
(TMR)
0.313
30
0.09 × t
(CHG)
0.360
0.414
100
s/Ω
kΩ
s
kΩ
t
(PRECHG)
I
(FAULT)
0.10 × t
(CHG)
0.11 × t
(CHG)
1
CHARGER SLEEP THRESHOLDS (ACPG , PG, and USBPG THRESHOLDS, LOW
POWER GOOD)
V
(SLPENT) (18)
Sleep-mode entry threshold
V
(UVLO)
V
I(BAT)
V
O(BAT-REG)
,
No t
(BOOT-UP)
delay
V
(UVLO)
V
I(BAT)
V
O(BAT-REG)
,
No t
(BOOT-UP)
delay
R
(TMR)
= 50 kΩ,
V
(AC)
or V
(USB)
or decreasing below
threshold, 100-ns fall time, 10-mv over-
drive
V
VCC
V
I(BAT)
+190 mV
V
VCC
V
I(BAT)
+125 mV
V
V
(SLPEXIT) (18)
Sleep-mode exit threshold
t
(DEGL)
Deglitch time for sleep mode
(19)
22.5
ms
START-UP CONTROL and USB BOOT-UP
t
(BOOT-UP)
Boot-up time
On the first application of USB input
power or AC input with PSEL Low (or
ISET3 low for bq24039)
120
150
180
ms
(16)
(17)
(18)
(19)
See Charger Sleep mode for ACPG (V
CC
= V
AC
) and USBPS (V
CC
= V
USB
) specifications.
To disable the safety timer and charge termination, tie TMR to the LDO pin.
The IC is considered in sleep mode when both AC and USB are absent (ACPG = USBGP = OPEN DRAIN).
Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the
switching specification.
7