bq2085-V1P3
SLUS598 − FEBRUARY 2004
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SMBUS TIMING SPECIFICATIONS
VDD = 3.0 V to 3.6 V, TA = −20°C to 85°C (unless otherwise noted)
PARAMETER
FSMB
FMAS
TBUF
THD:STA
TSU:STA
TSU:STO
THD:DAT
TSU:DAT
TTIMEOUT
TLOW
THIGH
TLOW:SEXT
TLOW:MEXT
SMBus operating frequency
SMBus master clock frequency
Bus free time between start and stop
Hold time after (repeated) start
Repeated start setup time
Stop setup time
Receive mode
Data hold time
Data setup time
Error signal/detect
Clock low period
Clock high period
Cumulative clock low slave extend time
Cumulative clock low master extend time
See (2)
See (3)
See (4)
See (1)
Transmit mode
TEST CONDITIONS
Slave mode, SMBC 50% duty cycle
Master mode, no clock low slave extend
4.7
4.0
4.7
4.0
0
300
250
25
4.7
4.0
50
25
10
35
ns
ns
ms
µs
µs
ms
ms
MIN
10
51.2
TYP
MAX
100
UNIT
kHz
kHz
µs
µs
µs
µs
TF
Clock/data fall time
See (5)
300
ns
TR
Clock/data rise time
See (6)
1000
ns
(1) The bq2085−V1P3 times out when any clock low exceeds TTIMEOUT
(2) THIGH Max. is minimum bus idle time. SMBC = 1 for t > 50
µs
causes reset of any transaction involving bq2085−V1P3 that is in progress.
(3) TLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) TLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time TR = (VILMAX − 0.15 V) to (VIHMIN + 0.15 V).
(6) Fall time TF = 0.9 VDD to (VILMAX − 0.15 V).
DATA FLASH MEMORY SWITCHING CHARACTERISTICS
VDD = 3.0 V to 3.6 V, TA = −20°C to 85°C (unless otherwise noted)
PARAMETER
t(RETENSION)
Data retention
Flash programming write-cycles
t(WORDPROG)
Word programming time
TEST CONDITIONS
See (1)
See (1)
See (1)
See (1)
14
MIN
10
105
2
16
TYP
MAX
UNIT
Years
Cycles
ms
mA
I(DDPROG)
Flash-write supply current
(1) Specified by design. Not production tested.
Register Backup
PARAMETER
I(RBI)
RBI data-retention input current (1)
TEST CONDITIONS
VRB > 3.0 V, VDD < VIT
1.3
MIN
TYP
10
MAX
100
UNIT
nA
V
V(RBI)
RBI data-retention voltage
(1) Specified by design. Not production tested.
6
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