AM6548, AM6528, AM6526
ZHCSLA7B –DECEMBER 2019 –REVISED JUNE 2021
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• Added MCSPI timing conditions table. Updated Timing Requirements and Switching Characteristics tables.....
207
• Updated MMCi Interface Timing Requirements, Switching Characteristics, and DLL Delay Mapping table.
Also added a Timing Conditions table. Also updated MMCSD speed support description.............................214
• (Timing Requirements for MMCi - DDR50 Mode) Added associated footnote for "j" value............................220
• Updated title from NAVSS to CPTS under Peripheral timing section. Added CPTS Timing Conditions table
and updated table format and descriptions of the parameters in Timing Requirements and Switching
Characteristics tables..................................................................................................................................... 222
• Added Timing Conditions table and DLL Delay Mapping table in OSPI. Updated timing requirements and
switching characteristics table limits. Renamed "No Loopback" mode to "Internal Clock" mode................... 224
• Updated min input slew rate for 3.3V DDR, Internal Pad Loopback mode to 2 V/ns. Updated input timing
limits for 3.3V DDR, DQS mode..................................................................................................................... 224
• Added note clarifying I/O timing is not applicable when OSPI is used with data training .............................. 224
• Added timing conditions and updated parameter descriptions under PRUsection. Added timnig requirements
and switching characteristics for 10 Mbps and 100 Mbps modes in RGMII mode. Updated timing limits for
SHIFT OUT, ECAP, UART modes.................................................................................................................. 231
• (PRU ICSSG Parallel Capture): Updated input hold time to 0.6 ns................................................................232
• (PRU ICSSG RGMII) Updated hold time for RXCTL and RD to 1.15 ns........................................................241
• Added Timing Conditions table in Debug Trace and removed rise/fall time parameters from Switching
Characteristics table and diagram.................................................................................................................. 247
• Added JTAG Timing Conditions table. Updated Timing Requirements and Switching Characteristics table
limits................................................................................................................................................................247
• Updated/Changed "MCU_OPSI[x]_LBCLKO" typo to "MCU_OSPI[x]_LBCLKO".......................................... 263
• (LVCMOS External Capacitor Connections): Updated/Changed the "All VDDSHV[8:0] and
VDDSHV[2:0]_WKUP supplies configured for 1.8V operation" image........................................................... 268
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