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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
MII1_RX_ER
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
K19
M19
N19
J19
J15
L18
K18
H16
gmii1_rxerr
rmii1_rxerr
spi1_d1
0
I
I
L
L
L
L
L
7
7
7
7
VDDSHV5 /
VDDSHV5
Yes
Yes
Yes
Yes
6
6
6
6
PU/PD
PU/PD
PU/PD
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I/O
I/OD
I/O
O
I2C1_SCL
mcasp1_fsx
uart5_rtsn
uart2_txd
O
gpio3_2
I/O
I
MII1_RX_CLK
MII1_TX_CLK
MII1_COL
gmii1_rxclk
uart2_txd
L
L
L
VDDSHV5 /
VDDSHV5
LVCMOS
LVCMOS
LVCMOS
O
rgmii1_rclk
mmc0_dat6
mmc1_dat1
uart1_dsrn
mcasp0_fsx
gpio3_10
I
I/O
I/O
I
I/O
I/O
I
gmii1_txclk
uart2_rxd
VDDSHV5 /
VDDSHV5
I
rgmii1_tclk
mmc0_dat7
mmc1_dat0
uart1_dcdn
mcasp0_aclkx
gpio3_9
O
I/O
I/O
I
I/O
I/O
I
gmii1_col
VDDSHV5 /
VDDSHV5
rmii2_refclk
spi1_sclk
I/O
I/O
I
uart5_rxd
mcasp1_axr2
mmc2_dat3
mcasp0_axr2
gpio3_0
I/O
I/O
I/O
I/O
38
Terminal Description
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